Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your profile.
Icon | Title | Posts | Recent Message Time Column |
---|---|---|---|
Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
| 95385 Posts | 04-23-2024 11:27 AM | |
FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
| 28898 Posts | 04-23-2024 12:45 AM | |
FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
| 27335 Posts | 04-23-2024 10:37 AM | |
Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
| 4957 Posts | 04-19-2024 10:46 AM | |
Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
| 2531 Posts | 04-22-2024 07:33 PM | |
Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
| 52769 Posts | 04-23-2024 10:53 AM | |
Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems
| 2532 Posts | 04-22-2024 12:52 AM | |
Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
| 82537 Posts | 04-23-2024 10:48 AM | |
Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
| 3531 Posts | 04-22-2024 10:44 PM | |
Intel® FPGA Software Installation & Licensing
Installation and Licensing that’s includes Intel Quartus® Prime software, ModelSim* - Intel FPGA Edition software, Nios® II Embedded Design Suite on Windows or Linux operating systems.
| 5719 Posts | 04-23-2024 01:50 AM | |
FPGA Wiki
Welcome to the Intel FPGA Wiki
| 364 Posts | 11-03-2022 01:29 PM |
by PrivateIsland Beginner in Programmable Devices 04-23-2024 0 5 | 0 | 5 | ||
0 | 5 | |||
by HamzahS New Contributor I in Nios® V/II Embedded Design Suite (EDS) 04-23-2024 0 1 | 0 | 1 | ||
by Broddo New Contributor I in Nios® V/II Embedded Design Suite (EDS) 04-23-2024 0 1 | 0 | 1 | ||
by kwt1 Beginner in Intel® Quartus® Prime Software 04-23-2024 0 7 | 0 | 7 | ||
by Joshuamem Beginner in FPGA, SoC, And CPLD Boards And Kits 04-23-2024 0 2 | 0 | 2 | ||
0 | 3 | |||
0 | 3 | |||
by jkhoo Employee in Programmable Devices 04-23-2024 0 2 | 0 | 2 | ||
0 | 2 | |||
0 | 3 | |||
by PedroJServian Beginner in Programmable Devices 04-23-2024 0 2 | 0 | 2 | ||
by anonimcs New Contributor I in Intel® Quartus® Prime Software 04-23-2024 0 0 | 0 | 0 | ||
by epissadakis Beginner in Programmable Devices 04-23-2024 0 2 | 0 | 2 | ||
by gustifix Beginner in FPGA, SoC, And CPLD Boards And Kits 04-23-2024 0 0 | 0 | 0 |
New edition CVGT Board just arrived from Terasic. My already working programming script fails by GordWait 04-22-2024 0 20 |
N6000-PL MAX10 Build by Beginner_in_FPGA 04-22-2024 1 19 |
NIOS II - FW doesn't work with compiler optimization turned on by naand 04-22-2024 0 15 |
Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.