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Beginners question in multiple assignments to output

FPGA_FR
Beginner
209 Views

Hi everyone,

I would be interested in assigning two wire variables to a single output pin and obtain as an output signal the summation of the two signals.

A trivial example would be to use the clock signal CLK_50 and NOT(CLK_50) and send them both to the same output to obtain a constant high-level voltage corresponding to the summation (not in the Boolean sense) of the two signals.

Do you know if this possible to combine signals to outputs this way ?

Thank you

Best,

0 Kudos
1 Solution
ak6dn
Valued Contributor III
199 Views

What you seem to be asking for is analog logic, summing the levels on two wires to produce an output signal that can have three discrete levels.

     IE:   (0,1) + (0,1) = (0,1,2)

This is not possible in digital logic FPGAs.

 

At best you could two outputs and resistors to simulate a simple digital to analog converter, much like some development boards support an analog VGA signal using an array of resistor values R-2R-4R-8R etc to make a simple D to A.

 

Can't be done internal to a device however. Not with any current Altera FPGA parts AFAIK.

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6 Replies
ak6dn
Valued Contributor III
200 Views

What you seem to be asking for is analog logic, summing the levels on two wires to produce an output signal that can have three discrete levels.

     IE:   (0,1) + (0,1) = (0,1,2)

This is not possible in digital logic FPGAs.

 

At best you could two outputs and resistors to simulate a simple digital to analog converter, much like some development boards support an analog VGA signal using an array of resistor values R-2R-4R-8R etc to make a simple D to A.

 

Can't be done internal to a device however. Not with any current Altera FPGA parts AFAIK.

SyafieqS
Moderator
189 Views

Hi FPGA_FR,

 

May I know if there is any update from previous reply?

 

FPGA_FR
Beginner
174 Views

Dear SyafieqS,

I have received an answer from ak6dn, which is ok with me and make sense.
Also, would it possible as a moderator that you are not using my first name from my account information but my username FPGA_FR in public post ? Is it possible to edit that out from your previous message ?

Thank you very much for your understanding on this matter.
Thank you all for your help on this forum.

Very much appreciated


Best wishes,

SyafieqS
Moderator
167 Views

Understood. Let me know if there is any other concern on this.


SyafieqS
Moderator
144 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 10/10 survey


FPGA_FR
Beginner
136 Views

Dear SyafieqS,

I have already reply in my post on November 11 that ak6dn solved the problem. The problem is already marked as "solved" in the feed, but somehow I cannot put any kudos to this user for the answer provided (I do not why it does not work).

Thank you again for your help and support.
Best wishes,

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