Triple speed Ethernet (TSE) MAC Configuration in 10/100 for Arria 10 device FPGA.

[deepag]

Hi ,

       Am Working on ARRIA 10 device FPGA (10AX016E3F27I2SG) . Using Quartus Standard edition version 21.1 for FPGA Design  and NIOS II  SDK for Software development. I have few Queries regarding the FPGA and its drivers.

1.   we have Configured NIOS Processor for Triple Speed Ethernet MAC in Quartus tool , and exported to NIOS II  tool. Ethernet Address and Board support Packages (BSP) got generated but , am unable to find the sequence of the TSE driver. I have attached the BSP (Source and Header )Files  generated for TSE. I need the sequence for TSE driver.

      a.   How to do Reset for MAC ?

      b. Need functions or routines for TSE Transmit and Receive Frames .

      c. Initialization process of TSE MAC ?

      d. How to Set the speed for TSE MAC ?

      e. Process to Enable and Disable the Interrupts of TSE MAC.

 2. I need Register set with Bit description and Offset Addresses for TSE MAC Initialization .

3. TCP IP stack and how to attach the driver to main function and process to send TCP and UDP Packets. 

4. I need the example code for TSE MAC configuration of 10/100.

5. We are using Microchip PHY (KSZ8081RNDCA-TR) in our custom board. I need sequence process to access the PHY .

[robert2001b]

The initialization process generally includes setting up the MAC with the correct operating parameters, which might involve configuring registers for control, speed, duplex mode, and other settings. To set the speed for the TSE MAC, you would write to the control registers to select between 10/100/1000 Mbps operation modes. This is often part of the initialization routine. The register set with bit descriptions and offset addresses for TSE MAC initialization can typically be found in the TSE MAC’s datasheet or technical reference manual. This document will list all the registers, their functions, and how to program them. Attaching the driver to the main function and processing TCP and UDP packets usually involves integrating the TSE MAC driver with your system’s TCP/IP stack. This might require configuring the stack to recognize the TSE MAC as a network interface and ensuring that the driver is properly initialized during system startup. 

[deepag]

Hi ,

   Thanks for the Response . Can you please give me the detailed information regarding the TSE MAC's driver which got generated to nios II SDK tool .  

 I have used tse_mac_SwReset(np_tse_mac *pmac) , alt_tse_phy_add_profile(alt_tse_phy_profile *phy), alt_tse_mac_set_speed(np_tse_mac *pmac, alt_u8 speed) these functions  . But, am unable to read back  the registers which are present inside these functions . 

0x00111000 this is the Mac address which got generated to NIOS II SDK tool. (0x02)Command Config  This is the offset in which Reset, Speed and duplex mode were present. I Have Set the Reset Bit according to the Command config Register description .But, It is unable to come out of Reset.   I have attached the Files in the last message. Can you please go through those files and tell me that these files will work or not?

 I have attached altera_avalon_tse.c file in which TSE MAC Driver  is there.

Please help me in this .

Thanks, 

Deepa 

[deepag]

Hello ,

        Am Working on ARRIA 10 device FPGA (10AX016E3F27I2SG) . Using Quartus Standard edition version 21.1 for FPGA Design  and NIOS II  SDK Tool for Software development.  Designed custom board embedded with this FPGA connect to Ethernet PHY(KSZ8081RNDCA-TR) .  I have created a project in Nios II SDK Tool where Board support Package ( BSP )Files generated .

  Am referring this  file ug_ethernet-683402-666815%20(3).pdf . to work on ethernet.

 1. I have gone through the function descriptions of page 195  ( tse_mac_raw_send() ). But, this function is not available in the NIOS II tool generated BSP Files. And we need tse_mac_raw_Receive  function also which is not available.

2. Can you please give the MAC INITIALIZATION  and PHY Management sequence or drivers .

3. Is there any special effort required to update ethernet driver  ?

 I have attached all the BSP Files related to ethernet ,which got generated in Nios II tool. Can you please tell us that these files are usefull or not .If it is ,then send the sequence process to work on ethernet driver.

    Thanks in advance , we are expecting fast response as we are in urgent need of this ethernet.

Thanks & regards ,

Deepa.G   

[ZiYing_Intel]

Hi,

We are not supporting driver modification because changing the setting might cause unexpected error which is not verified yet. User might need to modified by themselves by their own risk. Since we are not supporting driver modification, I now transition this thread to community support. Otherwise, the community users will continue to help you on this thread.

Best regards,

Zi Ying

[deepag]

Hi ,

  Thanks for the response . Can you please give us any example driver for Arria 10 or any other FPGA device which supports External PHY TSE Ethernet which is connected through MII to FPGA . I need Example driver for NIOS II SDK Tool . This would be helpfull for us to work on TSE . 

Thanks & regards ,

Deepa G

[deepag]

Hi , 

   Can you please send TSE Example  Driver which consists of  tse_mac_raw_send() ,tse_mac_raw_Receive()  function definitions.

 As these functions were mentioned in this Document Page.No - 195 ( ug_ethernet-683402-666815%20(3).pdf ) .

  Thanks in advance .

Best Regards ,

Deepa G.