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[FPGA USM]Issue in implementing zero-copy data transfer

giulio2
Beginner
169 Views

Hello everyone,

 

I'm trying to reproduce the zero-copy data transfer mechanism for a personal project.

The code compiles and runs on FPGA Emulator, so now I'm trying to compile and run on FPGA hardware with USM support(intel_s10sx_pac:pac_s10_usm) in devcloud.

The compilation goes fine, but when I have to run it gets stuck, this is strange to me since in FPGA Emulator it entirely runs and reproduces correct results, so I guess I am missing something about how to run code written for FPGA with usm support.

What I do is the following:

through devcloud_login I select an available strattix node, then I run:

aocl initialize acl0 pac_s10_usm

and finally I run the binary.

I'm also uploading a zip of the code containing the kernels.

Thank you in advance for your availability.

0 Kudos
5 Replies
BoonBengT_Intel
Moderator
141 Views

Hi @giulio2,


Thank you for posting in Intel community forum and hope all is well.

Clarification if I may, is this a custom design that you have self developed or is there a reference design that Intel have published?


If it is from us, it would be a great help if you are able to provide us the link to the reference design.

Hope to hear from you soon.


Best Wishes

BB


giulio2
Beginner
131 Views

Hello,

 

Thanks for your answer,

I was trying trying to adapt the zero-copy mechanism in my implementation of the hash join (in order to reduce the total latency).

I followed what is done in this tutorial, https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/Tutorials/D....

In my project I have included, as they are, the implementations of "unroller", "streaming data" and "tuple" that are present in your github repository.

https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/ReferenceDe...

As I said before if I compile for the FPGA emulator it works and provide correct results.

When I have to compile for hardware, I target in my CMake "intel_s10sx_pac:pac_s10_usm" as FPGA board, then I select a Strattix node through devcloud_login command, and submit the compilation job.

The compilation goes fine and I am also to generate the report.

To run the binary, I do the following:

-I select a Strattix node in an interactive way(using devcloud_login command)

-I run "aocl initialize acl0 pac_s10_usm"

-I run the binary ( here in runtime gets stuck)

By getting stuck, I mean it never produces the final results (same behavior when doing an infinite loop).

 

I tried to compile and run your zero-copy data transfer code(https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/Tutorials/D...) and it worked (it runs entirely). So I just don't understand what I'm doing wrong.

 

Thank you in advance for your availability.

 

giulio2
Beginner
126 Views

I am providing you the report generated for further clarification.

BoonBengT_Intel
Moderator
91 Views

Hi @giulio2,


Thanks for the explanation, yes design example of data transfer should be compliable.

As I do not have visibilities on how the implementation of data streaming and unroll are being done in the design example mention.

Here are some few resources that you can refer to for the mention topic:

- https://www.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide/top/opt... (streaming)

- https://www.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide/top/fla... (loop unrolling)


To further clarify, may I know where did you get the hash_join_fpga.hpp refences from?

Cheers, looking forward to hear from you.


Best Wishes

BB


BoonBengT_Intel
Moderator
55 Views

Hi @giulio2,


Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome, and will no longer monitor this thread. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.


Best Wishes

BB


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