Im using cycloneVsoc (BareMetal) and trying to transfer a massive amount of data from HPS to FPGA.
The thing is : if I use alt_write_xxxx() to transfer the data, there will be a big gap(around 2~3us) between two "write" orders.
I heard of burst write in avalon mm bridge but I didnt find any HWLIB support for that function.
The FPGA through SDRAM seems to be slower than the direct transfer.
So I want to know is there a way to read/write a massive data in a short period?
And How to do it.
after i investigate, unfortunately data can not come as a stream. It must be put to SDRAM
to do that the DMA maybe involve. This example is probably worth looking at, it's a bare metal program but it give you an idea what has to happen at a low level to communicate with the DMA core: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html
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