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How to use Avalon-ST to Avalon-MM in msgDMA

Balkesh
Beginner
450 Views

Hello Sir,

I want to know should i use Modular scatter Direct Memory Access IP in order to take coming data from Avalon Streaming and convert them to Avalon mm interface to store in memory. 

Should i need to write the descriptor or it automatically handle everything .

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wchiah
Employee
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Hi,


Avalon-ST (Streaming) interface is used for streaming data, while the Avalon-MM (Memory-Mapped) interface is used for memory-mapped transactions. When you want to transfer data from an Avalon-ST source to a memory location accessible via an Avalon-MM interface, you can use the Modular Scatter-Gather Direct Memory Access (MSGDMA) IP core provided by Altera.

The MSGDMA IP core is designed to handle data transfers between different types of interfaces and supports on-the-fly data movement without CPU intervention. It can be configured to handle transfers from Avalon-ST sources to Avalon-MM sinks.


Here's a high-level overview of how to use MSGDMA for transferring data from Avalon-ST to Avalon-MM:

  1. Instantiate the MSGDMA IP Core: You need to instantiate the MSGDMA IP core in your FPGA design. You can configure the MSGDMA IP core using the Intel Quartus Prime software, where you specify the interfaces and other parameters according to your design requirements.
  2. Configure the Descriptor Controller: The MSGDMA IP core uses descriptors to define the details of a DMA transfer, such as source address, destination address, transfer length, and control information. You will need to write descriptors to control the data transfer. The descriptors can be written by software running on a CPU or by another hardware component.
  3. Write Descriptors: Before the data transfer can begin, you need to write the descriptors that define the transfer. This includes setting up the source address (for Avalon-ST, this might be the base address of the data stream), the destination address (the memory location where the data should be stored), and the amount of data to transfer.
  4. Start the Transfer: Once the descriptors are written, you can start the transfer. The MSGDMA IP core will read the descriptors and handle the data transfer according to the specified parameters.
  5. Monitor and Manage the Transfer: You can monitor the transfer status through the MSGDMA control and status registers. If necessary, you can also manage the transfer by updating or adding descriptors, pausing, or aborting the transfer.
  6. Handle Interrupts: Optionally, you can configure the MSGDMA IP core to generate interrupts upon completion of a transfer or when certain events occur. This allows a CPU or other hardware component to respond to the transfer's progress or completion.


Based on my understanding, while the MSGDMA IP core automates the data transfer process, you still need to write the descriptors that define each transfer's parameters. The IP core does not automatically handle everything without some initial setup and control. The level of automation depends on how you configure and manage the MSGDMA IP core in your system


You may refer for our IP user guide for detail

Also there is a ready use mSGDMA example design


Let me know if that help you.


Regards,

Wincent_Intel



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wchiah
Employee
351 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

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Balkesh
Beginner
328 Views

Thanks for the help but actually I have not used HPS till now so can we use HPS for managing descriptors for MSGDMA IP as I want to store data coming in Avalon Streaming format and then storing in DDR using EMIF.
I have read user guide about MSGDMA IP but how to configure the C files for HPS or DMA transfer that i am not able to understand. Also the example design that you have provided in that i cant able to locate cv_datamover_ed.tar.gz file.
So can you provide a simpler example using HPS if possible.
I am using Agilex 7 board with 32 GB DDR.
Hoping for positive response.

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wchiah
Employee
248 Views

Hi,


May I know you are referring to Agilex I-series or F-series ?

If I series you can get it via https://www.rocketboards.org/foswiki/Documentation/HPSExampleDesignForAgilex7ISeriesDeKit2xRTileAnd1xFTile


Else you can try to generate the example via IP catalog. (if available)


Regards,

Wincent_intel



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wchiah
Employee
201 Views

Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

 

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.


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wchiah
Employee
151 Views

Hi 

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.  

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause 

Hence, This thread will be transitioned to community support.  

If you have a new question, feel free to open a new thread to get support from Intel experts.  

Otherwise, the community users will continue to help you on this thread. Thank you 

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences.  

 

Regards, 

Wincent_Intel 

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey. 


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