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Manual simulation of a HLS design failed

ettjaakko
Beginner
477 Views

We are trying to test HLS Compiler by building a simple component for matrix multiplying. The component works and simulates fine by running the co-simulation .exe file produced by the HLS Compiler.

However we are also trying to simulate manually in ModelSim using a verilog testbench (in which the component is instantiated) with NativeLink from Quartus, but the simulation fails with the errors:

 

# ** Error: (vlog-13069) c:/.../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v(21): near "acl_arb_data": syntax error, unexpected IDENTIFIER.

# ** Error: c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v(21): (vlog-13205) Syntax error found in the scope following 'interface'. Is there a missing '::'?

 

Intel HLS Compiler version 21.2.0 Build 68.1
Intel Quartus Prime Lite Edition Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
ModelSim Intel FPGA Started Edition 2021.1 Revision 2021.2.
Also tested with ModelSim Intel FPGA Started Edition 2020.1 Revision 2021.2.

 

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1 Solution
ettjaakko
Beginner
430 Views

Hello,

I'm replying to my own topic for resolving the issue. The problem was the .do file that is generated when executing NativeLink testbench from Quartus marks the source files generated by HLS Compiler as Verilog 2001 instead of SystemVerilog. Perhaps because the files are with the .v extension instead of .sv, even though they contain SystemVerilog specific code?

Replacing all of the -vlog01compat with -sv option in the .do file (and then running the .do file again in ModelSim) allowed the execution of the test bench.

E.g.:

vlog -sv -work work +incdir+C:/../dsp_hls_streams.prj/quartus {C:/../dsp_hls_streams.prj/quartus/quartus_compile.sv}
vlog -vlog01compat -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v}
vlog -vlog01compat -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_avm_to_ic.v}


Replace with -sv:

 

vlog -sv -work work +incdir+C:/../dsp_hls_streams.prj/quartus {C:/../dsp_hls_streams.prj/quartus/quartus_compile.sv}
vlog -sv -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v}
vlog -sv -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_avm_to_ic.v}



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3 Replies
Nurina
Employee
442 Views

Hi,


This happens because Quartus Prime Lite v20.1.1 does not support HLS. Try using Quartus Prime Lite v19.1 and install the HLS compiler for that version here: https://fpgasoftware.intel.com/19.1/?edition=lite&platform=windows


For your information starting from version 20.1, HLS is not supported on Quartus Standard and Lite edition. If you want to use HLS on the latest version you'll have to use the Pro edition.


Regards,

Nurina


ettjaakko
Beginner
431 Views

Hello,

I'm replying to my own topic for resolving the issue. The problem was the .do file that is generated when executing NativeLink testbench from Quartus marks the source files generated by HLS Compiler as Verilog 2001 instead of SystemVerilog. Perhaps because the files are with the .v extension instead of .sv, even though they contain SystemVerilog specific code?

Replacing all of the -vlog01compat with -sv option in the .do file (and then running the .do file again in ModelSim) allowed the execution of the test bench.

E.g.:

vlog -sv -work work +incdir+C:/../dsp_hls_streams.prj/quartus {C:/../dsp_hls_streams.prj/quartus/quartus_compile.sv}
vlog -vlog01compat -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v}
vlog -vlog01compat -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_avm_to_ic.v}


Replace with -sv:

 

vlog -sv -work work +incdir+C:/../dsp_hls_streams.prj/quartus {C:/../dsp_hls_streams.prj/quartus/quartus_compile.sv}
vlog -sv -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v}
vlog -sv -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_avm_to_ic.v}



Nurina
Employee
408 Views

Hi,

 

Glad your problem is solved and thank you for sharing your solution. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

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