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altera_fpga_manager ff706000.fpgamgr:timeout

Jai_Led__Tan
Beginner
573 Views

Hello, 

I am currently working with an Altera DE1-SoC FPGA board on OpenCL with MSEL set to 01010.
So, I was trying out a project from github with link 

https://github.com/Er1cZ/Deploying_CNN_on_FPGA_using_OpenCL ;

This project is about deploying CNN on FPGA using OpenCL on an Altera DE10-Nano. I tried out the steps provided in the project and I got stuck at the aocl command. 

I run  aocl program /dev/acl0 squeezenet.aocx


The result shown is 
aocl program: Running reprogram from /home/root/opencl_arm32_rte/board/c5soc/arm32/bin
altera_fpga_manager ff706000.fpgamgr: timeout


I do not know why this happen, because i tried other OpenCL examples and it work perfectly.
My question is what is the usual root cause of this and how can I solve it? Could it be due to a difference in the board and if so, any other way than changing the board?

Any feedback/pointers to potential solutions are very welcome.

Thanks

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1 Reply
Vassiliev__Andrei
573 Views

Hi Tan,

This message seems to indicate that the programming of the boot Flash for FPGA is failing at the address 0xff706000.

You can try to lower the frequency of the JTAG while it is programming Flash devive on DE10-Nano. I think command similar to the one mentioned in 

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

should do it.

Trying another card is an option too.

If these fail try to reach out to Terasic Tech support.

Andrei.

 

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