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oneAPI IP integration with Avalon Streaming input/output

DorianL
Novice
1,098 Views

Hi i'm new with oneAPI and I want to create an IP to export in Quartus and i wanted to know how to have Avalon Streaming input and output for my kernel to treat images and more generaly how to create interfaces to communicate with other components with Avalon interface. I don't know how to make the difference between pipes/accessors/etc... Thank you !

8 Replies
BoonBengT_Intel
Moderator
1,003 Views

Hi @DorianL.


Thank you for posting in Intel community forum with the interest in Intel oneAPI and hope all is well.

Would like to understand further on your request, which devices are you working with? Also what are the oneAPI version that you are having?

Hope to hear from you soon.


Best Wishes

BB


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DorianL
Novice
964 Views

Hi @BoonBengT_Intel ,

 

I'm working on simulation only for the moment, and my version of oneAPI is the latest so the 2024. I was just trying to understand how i could export IP from oneAPI to Quartus and the first thing i didn't understand was the connection interfaces with other IP, but I finally found an example on the Intel oneAPI Github to work on that. My goal is to produce IP with oneAPI that could be usefull in the futur in other projects, like image or audio processing.

The first thing is that I have an error each time i want to simulate a Kernel that include streaming interfaces, like Avalon_streaming. I can emulate but I can't simulate. The error come from the aoc_sim_generate_qsys.tcl and the function "add_component" that can't be executed thanks to the log file created during the compilation for simulation. Do you have an idea of what could be the issue ?

 

DorianL

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BoonBengT_Intel
Moderator
850 Views

Hi @DorianL,


Noted and thanks for the information, for the mention flow on the OneAPI it would be the IP authoring compilation flow which will allow custom IP design which will than integrated into platform designer.

More details can be found in the following getting started guide:

- https://www.intel.com/content/www/us/en/docs/programmable/749869/22-4/getting-started-with-oneapi-ip-authoring-18311.html


To add on, there are also example design available in the following link below, which will guide you through the flow:

- https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/Tools/platform_designer


As for the error mention would you be able to provide more details on the code or the details of the error which will be helpful for us to understand the situation.

Hope to hear from you soon.


Best Wishes

BB


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DorianL
Novice
818 Views

Hi @BoonBengT_Intel ,

 

Thank you for your answer, I will check those links to understand how to export the IP on Quartus. For the error, it occured when I tried to simulate a Avalon Streaming pipe. The TCL script named aoc_sim_generate_qsys.tcl is called during the compliation for simulation and even if I only have the Quartus Prime Lite, it should take that in count and use function like "set_instance". Instead of that, the script act like I have the Quartus Pro Edition and try to "add_component" wich is not possible with the free version of Quartus and causes errors. Correct me if I'm wrong but I should be able to simulate oneAPI Avalon Streaming pipe with Quartus Lite ? Thank you !

 

DorianL

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BoonBengT_Intel
Moderator
691 Views

Hi @DorianL,


Noted with thanks for the details explanation for the error, and you are right unfortunately the current IP authoring compilation flow are build and supporting only for Quartus Pro edition, hence the error that you are seeing could be part of that reason. Would recommend to try with Quartus Pro edition instead. Please do let us know if there is other things we could help with.

Hope that clarify.


Best Wishes

BB


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DorianL
Novice
676 Views

Hi @BoonBengT_Intel ,

 

I tried to simulate with a version of Quartus Prime Pro edition but I still have the same issue, I can't simulate Streaming pipes in my IPs whereas it is working when I use MMHost pipes or Conduit pipes. I tried to simulate with fpga_sim command the example "Vector_add" on the github oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison/pipes but it is not working, is it simulating for you ? Do you have an idea of what could be responsible of that ? Thank you !

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DorianL
Novice
568 Views

Hi,

 

I tried with the new version of oneAPI 2024.1 and it finally worked ! Thank you for your help.

 

DorianL

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BoonBengT_Intel
Moderator
454 Views

Hi @DorianL,


Great! Good to know that it is working now, with no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

Thank you for the questions and as always pleasure having you here.


Best Wishes

BB


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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