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Hello, all, I'm not sure if this is the right forum, but I figured HPCC guys might know the answer : we're trying to build an application with two PCI Express cards in a Dell 2950, which uses the 5000X MCH. The question is if the MCH will allow peer-to-peer writes.
I looked thru the MCH datasheet, but it doesn't come out and say it, though there are some hints. Can someone confirm if peer-to-peer is "officially" supported ? Does it provide normal, close-to-hardware latencies, or is it a wimpy path that's not meant for real heavy duty use ? Does using peer-to-peer detract from the hostor DRAM bandwidth (say if no-snoop is set in the write requests) ?
Please let me know,orif there is some other forum or method to get this info.
Regards, Jon Sreekanth, sreekanth@accoladetechnology.com
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Disappointing to see lots of views, but no replies to this topic. Please let me know if I should ask on some other forum, or if there is somebody at Intel who can help.
Regards, Jon Sreekanth, sreekanth@accoladetechnology.com
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