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ALTLVDS_RX wrong parallel data

Altera_Forum
Honored Contributor II
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Hello,  

 

I am using Quartus II 13.1 and the megafunction ALTLVDS_RX on cyclone V E. For the moment I didn't try on the FPGA, I am only doing Modelsim simulations. 

The input frequency is 25 MHz and the SERDES factor is 7. 

My problem is that when I follow the guideline to implement the Receiver function I have wrong parallel data at the output of the receiver. In fact it's like deserializer doesn't have time to deserialize the entire word in one parallel period because the missing data appears on the next clock edge. 

Here my clocks parameters for ALTVDS_RX using external PLL (Already try with internal PLL and this is the same result) : 

Rx_inclock : 175 MHz; phase shift 180°;Duty Cycle :50% 

Rx_enable : 25 Mhz; phase shift 257°;Duty Cycle :14% 

Parallel clock (Not in the ALTVDS_RX) : 25 MHz; Phase shift 334,3°; Duty Cycle : 57% (As the real input clock) 

 

Thanks for your help. 

 

Romain
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FGüla
Beginner
531 Views

Hi, I know it's been a while. But did you manage to solve the problem? I have the same problem.

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