About IO PLL

[Yamada1]

It would be helpful if you could tell me about the Advanced Parameter tab of the IOPLL Intel FPGA IP settings. PLL is in direct mode.

1) Is it correct to understand that C-Counter-0 Divide Setting is the PLL output frequency division ratio for the VCO frequency?

2) If 1) is correct, is it correct that if this is an odd value, the PLL output duty will not be 50%? Or does it mean that if C-Counter-0 Even Duty Enable is true, the duty will be corrected to 50%?

3) If the duty is corrected in 2), will it affect jitter performance?

Sorry for the basic question, but I would appreciate it if you could explain it to me.

[AqidAyman_Intel]

Hello,

May I know you are referring to what device for this IOPLL IP?

Regards,

Aqid

[Yamada1]

Thank you for your response.

The description was missing. very sorry.

The device used is 10AX115S2F45I1SG.

We apologize for the inconvenience, but it would be helpful if you could teach us.

[AqidAyman_Intel · Accepted solution]

Thank you for the device part number. Please refer to the answer below:

1. Yes, you are correct. The output clock frequency is the result of the VCO frequency divided by the counter value. Can refer to Figure 64 in below link https://www.intel.com/content/www/us/en/docs/programmable/683461/current/pll-architecture.html
2. For this one, I think we used to call it odd division factor, where we use a negative edge clock to normalize the duty cycle to 50/50. Another that, you can take a look on this link https://www.intel.com/content/www/us/en/docs/programmable/683845/current/address-bus-and-data-bus-setting-for-23451.html
3. I don't think it affect jitter; it simply uses a falling edge instead of rising edge. If it did affect jitter, we would have to produce a different jitter spec for when that even duty bit is enabled vs disabled. 

Regards,

Aqid

[Yamada1]

Thank you for answering.

The materials you provided were very helpful.

thank you.

[AqidAyman_Intel]

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