Avalon I2C (Master) Intel FPGA IP

[gomezramones]

Hi, I am trying to use Avalon I2C (Master) Intel FPGA IP in Qsys but I am not sure how to use the register in this module since there are Control Register to configure the speed or enable the core. ISER to enable ACK and others. 

Just to make sure, signals scl_in and sda_in is when the I2C module is reading and scl_oe and sda_oe when is writing, right? In other words, it is the same if I would declare sda :inout and scl : inout?

[JingyangTeh]

Hi

To interface with the IP, you could include the library and interface with the IP with the following function calls.

https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/fpga-i2c-host-core-api.html

You could refer to the link below on the pin definition.

https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/interface-13852.html

There are more information of the IP in the link below:

https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/fpga-i2c-host-core.html

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Since a solution have been provided and no feedback was received, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards

Jingyang, Teh