Avalon-MM Address alignment, Response and lock

[Basavakiran]

Hi,

I have few doubts related to avalon-MM properties from Datasheet. 
1) Not getting proper detail about "Response" signal.

2) Not getting full idea related to "Address align" property.

3) Feature of "lock" signal.

Last time we had a discussion with one of Intel expert on same platform but we didn't got proper things so Please any one from design Team in this chain then it will get clear.

For your reference, case ID number to my post: 05871175

If its possible then I can arrange a meeting so its clears fast.

Thanks & Regards

Basavakiran Hiremath 

[RichardTanSY_Intel]

The "response" and "lock" signals are self-explanatory in the user guide.

You can find more details about them in this link: [https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interface-signal-roles.html].

Regarding "Address align," I believe you are referring to Address Alignment.

You can learn more about it here: [https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/mm-agent-addressing.html].

If you need further information, I recommend checking out this video which provides a comprehensive overview of the signal roles in the Platform Designer standard interfaces, specifically in Section 11 - Avalon@ Memory Mapped Interface. Section 11.19 covers the topic of Default Address Alignment, which may be of interest to you: [https://learning.intel.com/developer/learn/course/836/play/1507:100/platform-designer-standard-interfaces].

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

[RichardTanSY_Intel]

Dropping a note to ask if my last reply was helpful to you?

Do you need any further assistance from my side? 

Best Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support.

We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to let us know.

Thank you for reaching out to us!

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

[Basavakiran]

Hi Richard,

I have few doubts related to "Response" signals.
from Specification sheet I got what are the errors but I want to understand on which condition those errors will get generates these kind of details not present in Specification Sheet (Specially slverr).

If you provide some time for short meeting then which helps me lot.

Thanks & Regards
Basavakiran Hiremath

[RichardTanSY_Intel]

Sure, I have sent you an email with the meeting setup details. Please kindly check your email.

Best Regards,

Richard Tan

[SyafieqS]

Hello Basava,

Richard is on vacation. I am supporting temporary this issue.

I will address your issue in the email loop.

[Basavakiran]

Hello Syafieq,

I sent list of questions on 14th July, 2023.
still I didn't received any response from your end, Please try to help me.

Thanks & Regards
Basavakiran Hiremath

[SyafieqS]

I have response to your email thread.

[RichardTanSY_Intel]

As further inquiries is discussed in the email loop, I will transition this thread to community support.

If you have any further questions or concerns, please don't hesitate to reach out to us.

Thank you.

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.