Avalon pipelined burst read

[Altera_Forum]

I am trying to develop an interface to a Cypress USB chip. I've done this using a custom sopc component which is an AvalonMM slave and a standard SGDMA component. In my Nios code I call alt_avalon_sgdma_do_sync_transfer() to copy usb data from the Cypress device into SDRAM.  

 To maximise throughput, my custom component uses pipelined transfers with a read latency of 3 clock cycles. This allows one byte of usb data (the data bus with the cypress chip is 8-bit) to be clocked in on each clock cycle.  This was all working fine with small usb message sizes (<250 bytes). If I increase the usb message size to 512 bytes the received data in SDRAM contains byte errors. Using SignalTap I traced this problem to the fact that for larger message sizes the SGDMA<->Custom component is not master of the avalon bus for the full 512 byte message length. Due to the pipelining of usb data in the custom component, any break in read operations causes data to be lost.   I suspect, although I'm not certain, that the reason the break in read operations occurs is because the SGDMA read FIFO becomes full - it is set at the maximum value of 64 bytes.  My question is what is the best way of solving this problem? I can see two potential solutions:  1) Redesign the custom component hdl to handle the pipeline correctly when reads are stopped and resumed.  2) Use Avalon burst reads to guarantee mastering of the bus until all 512 bytes have been read.  I think that (2) is the preferable solution, but I'm not sure that it is possible because I can't find any examples of setting up avalon burst reads using the SGDMA block. For instance how do I setup the burstcount variable for a transfer?  Any advice on this would be greatly appreciated.

[Altera_Forum]

Wouldn't it be easier to just write your own little avalon memory mapped master that did the writing into memory for you instead of using the SGDMA? Then you could write your master to support bursts. 

 Jake