Clock missing from Timing Analyzer - Report Setup Summary

[Mikexx]

I have a clock mux along the lines in "ug-qps-03-design-recommendations.pdf"

I have set the output clock to be a Global Clock in the Assignment Editor and I give it's minimum period in the sdc file. I don't get any warnings of this signal in the fitter report. It is sent to an output pin as well as used internally.

However the clock is not mentioned in the Report Setup Summary whereas the other clocks of interest are.

I've tried a couple of variations of changing name and assigning the output clock to the internal name.

Any ideas where I might be going wrong?

[ShengN_Intel]

Hi,

If create the clock in the timing analyzer, and use the auto-generated .sdc. Will it reflected?

Thanks,

Regards,

Sheng

[Mikexx]

Many thanks for your reply.

I haven't made any changes to the Assignment Editor, but deleted/renamed the old sdc file and created a new one from Timing Analyzer.

These are now the active lines in the sdc file:

**************************************************************

create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {HDMI_TX_CLK} -period 6.750 -waveform { 0.000 3.375 } [get_ports {HDMI_TX_CLK}]

set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]

set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_hd9:dffpipe19|dffe20a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_gd9:dffpipe13|dffe14a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_rd9:dffpipe8|dffe9a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_qd9:dffpipe5|dffe6a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_pd9:dffpipe8|dffe9a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_od9:dffpipe5|dffe6a*}]

**************************************************************

After compiling the design which fitted fine and very quickly, I reopened Timing Analyzer, "Read the SDC File", double clicked "Report Setup Summary" and got a single line:

altera_reserved_tck 7.788 0.000

I am using SignalTap where the clock is also the missing clock HDMI_TX_CLK. SignalTap works as expected. The fitter report says it found "2 clocks" consistent with the SDC file. There are some expected warnings from not specifying the periods of input clocks that are specified in PLLs.

One thing that bothers me is this line and is mentioned 5 times in the processing messages:

   Info (13166): Register RX_Video:RX_Video_1|RX_Toggle is being clocked by CLK_50_Bank7A

CLK_50_Bank7A is the input clock feeding the PLLs, where a couple are used to created clocks that are muxed onto HDMI_TX_CLK.

In the design Register RX_Video:RX_Video_1|RX_Toggle is being clocked by another clock that are muxed in the same way as HDMI_TX_CLK.

[Mikexx]

Many thanks for your reply.

Second attempt at posting!

I haven't made any changes to the Assignment Editor, but deleted/renamed the old sdc file and created a new one from Timing Analyzer.

These are now the active lines in the sdc file:

**************************************************************

create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {HDMI_TX_CLK} -period 6.750 -waveform { 0.000 3.375 } [get_ports {HDMI_TX_CLK}]

set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]

set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_hd9:dffpipe19|dffe20a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_gd9:dffpipe13|dffe14a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_rd9:dffpipe8|dffe9a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_qd9:dffpipe5|dffe6a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_pd9:dffpipe8|dffe9a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_od9:dffpipe5|dffe6a*}]

**************************************************************

After compiling the design which fitted fine and very quickly, I reopened Timing Analyzer, "Read the SDC File", double clicked "Report Setup Summary" and got a single line:

altera_reserved_tck 7.788 0.000

There was no line in the table indicating HDMI_TX_CLK

I am using SignalTap where the clock is also the missing clock HDMI_TX_CLK. SignalTap works as expected. The fitter report says it found "2 clocks" consistent with the SDC file. There are some expected warnings from not specifying the periods of input clocks that are specified in PLLs.

One thing that bothers me is this line and is mentioned 5 times in the processing messages:

   Info (13166): Register RX_Video:RX_Video_1|RX_Toggle is being clocked by CLK_50_Bank7A

CLK_50_Bank7A is the input clock feeding the PLLs, where a couple are used to create 4 clocks that are muxed onto HDMI_TX_CLK.

In the design Register RX_Video:RX_Video_1|RX_Toggle is being clocked by a clock that selected from1 of 4 clocked the same way HDMI_TX_CLK is created.

[sstrell]

So HDMI_TX_CLK is an output clock you are creating and you say it is being used to clock internal logic as well?

Run Report Clocks, not a setup summary, to verify clocks in your design.  If it's not showing up in setup summary, that means it's not clocking anything internally.

[Mikexx]

Many thanks.

The "Report Clocks" does list this clock as I would expect.

HDMI_TX_CLK, or some variant of it, is clocking a lot of logic other pins are dependent on this and are behaving as expected. The same signal is used throughout the design so how can I check that setup and hold times aren't violated?

[sstrell]

What are all those false paths you've created?  Are you preventing analysis on the paths that are clocked by HDMI_TX_CLK?

Run Report Timing and specify you're looking for paths clocked by this clock.

[Mikexx]

Those false paths were the ones setup in Timing Analyzer by default and placed in the sdc file. All I did was add HDMI_TX_CLK into the "Create Clock" group in the sdc file.

I have no idea why it would do that and I don't recognise the names.

[sstrell]

So you should run detailed timing reports with Report Timing, setting the launch or latch clock as HDMI_TX_CLK to find paths clocked by this clock domain.

[Mikexx]

Thanks.

If I go to Custom Reports -> Report Timing I an enter HDMI_TX_CLK into the from and to clock. These exist in the pull-down option.

I placed * in the targets entry, leave it blank, or add all registers in the design. I get "Nothing to report" for all options. 

Not sure if it makes a difference bu I'm using Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition

[Mikexx]

An extract of the RTL Viewer demonstrates the clock goes to internal logic as well as an I/O pin.

[sstrell]

If you put the same clock in both From and To, it will only show paths in that clock domain, which it seems there aren't any.  Put it in only one or the other.

[Mikexx]

Many thanks for the idea.

There are many registers clocked by HDMI_TX_CLK with signals that feed registers with the same clock such as pipes.

I have tried leaving blank or with " * " with only a HDMI_TX_CLK  in the To and From fields. I always get "Nothing to report".

[ShengN_Intel]

Hi,

The clock HDMI_TX_CLK is your output clock right? Have you correctly constraint your input clock?

Take a simple clock divider example, if correctly constraint the input clock, the setup and hold of the output clock can be seen.

Thanks,

Regards,

Sheng

[Mikexx]

I'm sorry, I don't quite follow the philosophy.

The HDMI_TX_CLK is the output from a clock multiplexer that is fed by a couple of PLLs producing a total of 4 clocks, namely standard video clocks, the fastest being 150MHz.

The clock signal feeding the PLLs is a single 25MHz clock. 

[sstrell]

Do all the clocks of the PLL (input reference, output clocks) appear in the clocks report (Report Clocks)?

[ShengN_Intel]

Hi,

I guess you have create clock for your input clock and derive the pll clock.

In the timing analyzer, can you leave the From clock and To clock blank.

Then in Targets section, in either the From or To column search the HDMI_TX_CLK i think may be using get_keepers.

After that report timing.

Thanks,

Regards,

Sheng

[Mikexx]

Sorry for the late reply. Holidays get in the way of work, plus a rush project.

If I go to:

Timing Analyzer -> Constraints -> Set Maximum Delay -> From -> click on 3 dots

Collection -> get_clocks

Filter -> *HDMI_TX_CLK*  (with asterisks)

List

I can see 1 match of HDMI_TX_CLK

Hope this helps.

[ShengN_Intel]

Hi,

May I know you able to report the timing?

Thanks,

Regards,

Sheng

[Mikexx]

Sorry, I'm not sure what you're asking for.

[ShengN_Intel]

Hi,

May I know does your problem resolved ady?

Thanks,

Regards,

Sheng