Custom-PHY Error in Qsys

[himeno]

Hi,

The following error is occurring on QSYS of Quartus Prime.

Could you please tell me how to avoid the error?

[composition]

QSYS implements CustomPHY (xcvr_custom_phy_0), Reconfig macro (alt_xcvr_reconfig_0), and reset controller (xcvr_reset_controller).

FPGA:Cyclone V GT(5CGTD5)

Quartus Prime version:17.0.0 Build 595

[Error content]

Synchronization Clock (tx_clkout1) for CustomPHY input signal pll_powerdown1 cannot be found.

[My opinion]

I think pll_powerdown1 does not need to be synchronized with tx_clkout1

[sstrell]

Every interface in a component, custom or otherwise, must be synchronous to a clock interface.  I see tx_clkout0 in your screenshot, not tx_clkout1, so perhaps you did not create that clock interface.

If you think it should not be synchronous to that clock (it's just asynchronous control signals), you could set it as a conduit interface instead of a streaming sink.

[himeno]

Thank you for your advice.

>If you think it should not be synchronous to that clock (it's just asynchronous control signals), you could set it as a conduit interface instead of a streaming sink.

I would like to change only pll_powerdown0/1 to conduit interface.
If you know, could you please tell me?

[sstrell]

This is set on the Signals & Interfaces tab of the Component Editor.  Right-click your custom component in the IP Catalog and select Edit to reopen the Component Editor.

[himeno]

thank you.

Maybe there is a misunderstanding.

The error is not the IP that I created using the component editor, but the Custom PHY IP that was automatically generated using the IP catalog.

Even in that case, can I change from "streaming sink" to "conduit interface"?

[Kshitij_Intel]

Hi,

Can you please share your current observation and issue.

Thank you,

Kshitij Goel

[himeno]

Hi

The issue remains unresolved.
The issue listed at the top of this page still exists.

I am using CustomPHY IP (xcvr_custom_phy_0) on QSYS,
The following error has occurred.

>[Error content]
>Synchronization Clock (tx_clkout1) for CustomPHY input signal pll_powerdown1 cannot be found.

Could you please give me some advice?

Thank you,
Himeno

[Kshitij_Intel]

Hi,

Can you please share your design with steps mentioned to reproduce the issue.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel