Cyclone V GX and alt_iobuff_diff

[ProgAddicted]

I'm developing a LPDDR2 controller for Cyclone V GX Starter kit and i have problems with DQS differential bidirectional interface: using ALT_IOBUF_DIFF i get an error message "..Primitive ALT_IOBUFF_DIFF is not supported for the selected family (Cyclone V)".

DQS pins are set in Pin Planner as "I/O standard Differential 1.2-V HSUL", as suggested by the doc.

What is the correct way? 

(Quartus Prime Lite Edition 21.1.1, Verilog, Cyclone V GX Starter kit)

Grazie!

[sstrell]

You probably should be using ALTDDIO: https://www.intel.com/content/www/us/en/docs/programmable/683148/17-0/double-data-rate-i-o-altddio-in-and-54289.html

[ProgAddicted]

Tanks for the reply.

Unfortunately ALTDDIO only deals with Double Data Rate and not with bidirectional DIFFERENTIAL pins.

I will use ALTDDIO for Data and Address pins, but i need a solution for differential bidirectional DQS pins.

Any idea?

[FvM]

Hi,
are you explicitely instantiating ALT_IOBUF_DIFF? If so, why?

[Farabi]

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[Farabi]

Hello,

You should not use the primitive ALTIO_BUFF_DIFF directly as this is not the correct approach.

You should use Differential 1.2V HSUL for DQS signals.

Cyclone V devices are typically paired with the Intel UniPHY IP to implement memory interfaces, including LPDDR2.

The UniPHY controller automatically handles differential DQS signals and takes care of timing calibration and bidirectional operations.

If you’re not already using the UniPHY IP, consider generating the LPDDR2 interface using the DDR2/DDR3 SDRAM Controller with UniPHY IP in Quartus.

regards,

Farabi