Cyclone V device LVDS IO standard error in Quartus 18.1 version

[DV_Cap]

Hi,
I am trying to set one of my differential clock output to LVDS IO standard in 5CEBA7F27C8 cyclone V device and getting the following error 

I have set the IO standards of the clock as below
set_instance_assignment -name IO_STANDARD LVDS -to CC_OUTCLK_P
set_instance_assignment -name IO_STANDARD LVDS -to CC_OUTCLK_N

Trying to map these pins to 
PIN_J25 -to CC_OUTCLK_P
PIN_J26 -to CC_OUTCLK_N

As per one of the forums response I have removed the CC_OUTCLK_N pin assignment as Quartus can automatically assign the negative clock assignment 
community.intel.com/t5/Programmable-Devices/Error-169175-Pin-with-LVDS-I-O-standard-needs-a-differential/m-p/265868#M69142

This is the error message:
Error (21179):Pins CC_OUTCLK_P and CC_OUTCLK_N form a differential pair and uses pseudo-differential output node upd3_vid_clk:u_upd3_vid_clk|alt_io_obuf:u_cyclonev_io_obuf|alt_io_obuf_iobuf_out_h5u:alt_io_obuf_iobuf_out_h5u_component|pseudo_diffa. However, these pins also have an I/O standard LVDS that cannot be supported by the pseudo-differential output node.

Please help 

[Farabi]

Hello,

1. Is it possible to share the simple design so we can replicate the issue at our end?
2. Can try later version of Quartus?

regards,

Farabi

[Farabi]

Hello,

n-channel for LVDS pin will be created automatically by Quartus Pin Planner. You only need to assign this pin to physical pin number either through global assignment or using pin planner manually.

regards,

Farabi