Cyclone VGX Error(175012)

[Altera_Forum]

Hello All, 

 I have started pin assignment for one of the design , selected Device is cyclone v gx. when i have assigned clock pin to one pin location using pin_assignment window , the quartus while running fitter come out with an error stating   Error (175012): There are no HSSI reference clock input locations on the device that are compatible with the region constraints on the following logic.  Info (175015): The I/O pad is constrained to the location PIN_L8 due to: User Location Constraints (PIN_L8)  Info (175028): The HSSI reference clock input name: HSSI_REFCLK_CLUSTER0~Clk78~input~FITTER_INSERTED  while the pin has following properties    8A VREFB8AN0 IO CLK8p,FPLL_TL_FBp  DIFFIO_RX_T57p DIFFOUT_T57p L8       even searched google regarding the solution but coulnt find answer.   Does anyone knows how to resolve it???

[Altera_Forum]

34 views but still no answers...i think no one ever encountered this problem????

[Altera_Forum]

**solved the cause of proble 

The error arises due to the fact that clock pin which i was using was also mapped to transceiver referance clock pin and as transceiver referance clock pin is  differntial in nature and it requires dedicated refclock pin that are set to be used for transceiver.  But now my querry is whether a single ended clock be used for reference clock of a transceiver function which is generated from megawizard.???????