DE5aNet-DDR4 opencl17.1 setup question

[Altera_Forum]

I"m trying to set up my DR5aNet DDR4 FPGA board. I installed OpenCL and Quartus Prime properly, following the manual. But the problem is I cannot compile a test project of fft1d.cl into fft1d.aocx. 

 My setup specification is here.  CentOS 7.0.1406 linux kernel 3.10.0-123.20.1.el7.x86_64 aoc -version: Version 17.1.0 Build 240 aocl version: aocl 17.1.0.240 Licensed Quartus prime 17.1.0 Build 240  And I got following errors after executing this command `aoc device/fft1d.cl -o bin/fft1d.aocx -fpc -no-interleaving=default -board=de5a_net_ddr4 -v`. aoc: Environment checks are completed successfully. aoc: If necessary for the compile, your BAK files will be cached here: /var/tmp/aocl/ You are now compiling the full flow!! aoc: Selected target board de5a_net_ddr4 aoc: Running OpenCL parser.... aoc: OpenCL parser completed successfully. aoc: Optimizing and doing static analysis of code... aoc: Linking with IP library ... Checking if memory usage is larger than 100% aoc: First stage compilation completed successfully. Compiling for FPGA. This process may take a long time, please be patient. Error (17941): The design could not be loaded due to errors. Error: design::import_design -file base.qdb -overwrite failed! Error (23031): Evaluation of Tcl script /opt/intelFPGA_pro/17.1/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 3 errors, 4 warnings Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings Error: Compiler Error, not able to generate hardware  In addition, this is `bin/fft1d/quartus_sh_compile.log`  Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sun Jul 15 20:54:30 2018 Info: Command: quartus_cdb top -c base --import_design --file base.qdb --overwrite Info: Quartus(args): --project top -c base --file base.qdb --overwrite Info: Using INI file /root/intelFPGA_pro/17.1/hld/board/de5a_net_ddr4/tests/fft1d/bin/fft1d/quartus.ini Info: Running design::import_design -file base.qdb -overwrite Critical Warning (18639): Skipping database version check for import of database files from 'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software. Critical Warning (18639): Skipping database version check for import of database files from 'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software. Critical Warning (18639): Skipping database version check for import of database files from 'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software. Critical Warning (18639): Skipping database version check for import of database files from 'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software. Info (16677): Loading final database Info (16734): Loading "final" snapshot for partition "root_partition". Error (17941): The design could not be loaded due to errors. Error: design::import_design -file base.qdb -overwrite failed! Error (23031): Evaluation of Tcl script /root/intelFPGA_pro/17.1/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 3 errors, 4 warnings Error: Peak virtual memory: 2525 megabytes Error: Processing ended: Sun Jul 15 21:13:13 2018 Error: Elapsed time: 00:18:43 Error: Total CPU time (on all processors): 00:18:46 Info: ******************************************************************* Info: Running Quartus Prime Compiler Database Interface Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sun Jul 15 20:54:29 2018 Info: Command: quartus_cdb -t import_compile.tcl Info: Using INI file /root/intelFPGA_pro/17.1/hld/board/de5a_net_ddr4/tests/fft1d/bin/fft1d/quartus.ini Info: Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined Info: INTELFPGAOCLSDKROOT=/root/intelFPGA_pro/17.1/hld Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 777 megabytes Error: Processing ended: Sun Jul 15 21:13:13 2018 Error: Elapsed time: 00:18:44 Error: Total CPU time (on all processors): 00:18:46  Thanks in advance for your help!

[Altera_Forum]

The 17.1 BSP for the DE5a-Net board only works for the board variant that has the "10AX115N2F45E1SG" FPGA. If you have the other variants (10AX115N3F45I2SG, 10AX090N3F45I2SG), you should stick to v16.1 or ask Terasic to update their BSP for those variants.

[Altera_Forum]

Thank you, HRZ. 

My FPGA is 10AX115N2F45E1SG so do you have any idea to solve this? I could compile it on v16.1 but I still want to work on v17.1. any ideas would be appreciated.

[Altera_Forum]

Actually I made a mistake, the multiple variants is for the DDR3 version of the board, you seem to be using the DDR4 version which only has one variant. Anyway, Terasic's BSPs generally lack proper testing and new versions are regularly problematic; this could be just another failure on their part to properly test their BSP before releasing it. Based on your logs, the process is failing when Quartus is trying to import the BSP which is likely due to an issue with the BSP itself. I recommend contacting Terasic directly since only they can address BSP-related issues.

[Altera_Forum]

Thank you for your quick reply and the advice. I asked to fix the BSP and I would use DDR3 board while they are working on the driver.