Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Does QSYS support custom types?

Altera_Forum
Honored Contributor II
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Hello all,  

 

Does QSYS support custom signal types? Specifically, I am trying to create a custom component in my Avalon memory mapped system, and have this component act as a slave. I would also like to export an array of signals from this custom slave to access the array elsewhere in my design. When I try to "analyze synthesis files" in the component editor, I recieve an error saying :  

 

"Error: Verilog HDL or VHDL XML Interface error at *custom_block*.vhd(91): port "array_name" has an unsupported type" 

 

I have the array type defined in a package, and I am including this package in my list of synthesis files in the component editor, but am still recieving this error. Is this an unsupported feature of QSYS? I can't seem to find a clear answer in QSYS documentation.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hello all,  

 

Does QSYS support custom signal types? Specifically, I am trying to create a custom component in my Avalon memory mapped system, and have this component act as a slave. I would also like to export an array of signals from this custom slave to access the array elsewhere in my design. When I try to "analyze synthesis files" in the component editor, I recieve an error saying :  

 

"Error: Verilog HDL or VHDL XML Interface error at *custom_block*.vhd(91): port "array_name" has an unsupported type" 

 

I have the array type defined in a package, and I am including this package in my list of synthesis files in the component editor, but am still recieving this error. Is this an unsupported feature of QSYS? I can't seem to find a clear answer in QSYS documentation. 

--- Quote End ---  

 

 

No, Qsys only knows std_logic_vectors. Actually under the cover Qsys uses Verilog.  

So if you use (as I do) custom types in your Qsys blocks you will have to write the 2 necessary conversion functions: to_std_logic_vector( t : my_vhdl_type ) return std_logic_vector and its companion to_my_vhdl_type( v : std_logic_vector ) return my_vhdl_type. If you put the definitions of the type and the functions in a VHDL package you can use them throughout your Qsys components.
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Altera_Forum
Honored Contributor II
665 Views

 

--- Quote Start ---  

No, Qsys only knows std_logic_vectors. Actually under the cover Qsys uses Verilog.  

So if you use (as I do) custom types in your Qsys blocks you will have to write the 2 necessary conversion functions: to_std_logic_vector( t : my_vhdl_type ) return std_logic_vector and its companion to_my_vhdl_type( v : std_logic_vector ) return my_vhdl_type. If you put the definitions of the type and the functions in a VHDL package you can use them throughout your Qsys components. 

--- Quote End ---  

 

 

Thanks for the quick reply and for the information. I was able to work around this by creating conversion functions.
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