Enabling Avalon MM Transfers with Flow Control

[Altera_Forum]

I'm new to FPGA development so be gentle. 

 I have a question about how to enable flow control transfers between Avalon MM components.  The following passages from the Quartus II 8.0 Handbook seem to imply that one ought be able to connect two Avalon MM flow control capable components such as a SPI controller and a DMA, and have the DMA automatically transfer incoming data from the SPI interface at its supported data rate.  In Chapter 7. spi core of the Quartus II Handbook (NII51011-8.0.0) the following passage appears: the core’s avalon-mm interface is capable of avalon-mm transfers with flow control. the spi core can be used in conjunction with a dma controller with flow control to automate continuous data transfers between, for example, the spi core and memory. In Chapter 22. dma controller core of the Quartus II Handbook (NII51006-8.0.0) the following passage appears: the dma controller transfers data as efficiently as possible, reading and writing data at the maximum pace allowed by the source or destination. the dma controller is capable of performing avalon transfers with flow control, enabling it to automatically transfer data to or from a slow peripheral with flow control (for example, a universal asynchronous receiver/transmitter [uart]), at the maximum pace allowed by the peripheral.  the source and destination may be either an avalon-mm slave peripheral (i.e., a constant address) or an address range in memory. the dma controller can be used in conjunction with peripherals with flow control, which allows data transactions of fixed or variable length. the dma controller can signal an interrupt request (irq) when a dma transaction completes. a transaction is a sequence of one or more avalon transfers initiated by the dma controller core.  both the read and write master ports are capable of performing avalon transfers with flow control, which allows the slave peripheral to control the flow of data and terminate the dma transaction. My question is how does one enable flow control between two Avalon MM components (a SPI and DMA controller in this case)? I don't see any specific options in SOPC Builder that indicate that flow control is automatically enabled when they are connected.  It would be great if someone could provide an example or point me to one on the Altera site.  Thanks everyone.

[Altera_Forum]

I think you get this flow control automatically. In the Avalon Interface Specifications document, Table 3.1, "Avalon-MM Slave Port Signals", lists readyfordata and dataavailable as flow control signals. When I connected an SPI core to a DMA controller with default settings, the SPI controller drove these two signals to the DMA.

[Altera_Forum]

Brad is correct. Flow control in Avalon is determined by the physical signals the interface supports. Note however that you can get problems by connecting slaves that support flow control to masters that do not.

[Altera_Forum]

Thanks guys!