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Good day,
I am running some tests on power consumption for an Agilex 7 board on Quartus Prime Pro 24.2.
While running Power Analyzer without an input file is fine, when I introduce the .vcd file the software errors out and "quits unexpectedly".
More information about the error is collected below.
Is this a known issue, and if so, is there a known solution?
Thank you and regards, Noah
This is the last message on the "Processing" tab in Quartus:
Info(20170): Starting scan of VCD file ../verification/tb/sim/wlf2vcd.vcd (0 ns to End of File) for signal static probabilities and transition densities
This is what appears in the TCL command window:
Error:ERROR: run_flow_command with specified flow 'compile' failed: "Internal Error".
Error: while executing
Error:"flng::run_flow_command -flow "compile" -end "power" -resume"
This is the Quartus problem report:
Problem Details
Error:
*** Fatal Error: Access Violation at 00007FFABF479416
Module: quartus_pow.exe
Stack Trace:
Quartus 0x29415: PFIO_VCD_PARSER_EVENT_HANDLER::handle_upscope + 0x155 (POWER_PFIO)
Quartus 0x543a: pfio_vcd_parser_yyparse + 0x3da (POWER_PFIO)
Quartus 0x5041: pfio_vcd_invoke_parser + 0x71 (POWER_PFIO)
Quartus 0x39ef6: PFIO_VCD_READER_MAIN::load_signal_statistics_from_vcd_files + 0x8f6 (POWER_PFIO)
Quartus 0x9ae74: PAN_UTILITY_IMPL::load_putil_sa_data_from_file + 0x444 (POWER_PAN)
Quartus 0x9b157: PAN_UTILITY_IMPL::load_sa_data + 0x77 (POWER_PAN)
Quartus 0x14f2e: PAN_MAIN_IMPL2::run_flow + 0x28e (POWER_PAN)
Quartus 0x6568d: pan_start + 0x1d (POWER_PAN)
Quartus 0x4532: QPOW_FRAMEWORK::execute + 0xc2 (quartus_pow)
Quartus 0x20fef: qexe_do_normal + 0x1af (comp_qexe)
Quartus 0x299e3: qexe_run + 0x6a3 (comp_qexe)
Quartus 0x2abd6: qexe_standard_main + 0x266 (comp_qexe)
Quartus 0x560c: qpow_main + 0x6c (quartus_pow)
Quartus 0x28418: msg_main_thread + 0x18 (ccl_msg)
Quartus 0x295f2: msg_thread_wrapper + 0x82 (ccl_msg)
Quartus 0x2b063: mem_thread_wrapper + 0x73 (ccl_mem)
Quartus 0x261df: msg_exe_main + 0x17f (ccl_msg)
Quartus 0x72cb: __scrt_common_main_seh + 0x10b (quartus_pow)
Quartus 0x1257c: BaseThreadInitThunk + 0x1c (KERNEL32)
Quartus 0x5af07: RtlUserThreadStart + 0x27 (ntdll)
End-trace
Executable: quartus
Comment:
None
System Information
Platform: windows64
OS name: Windows 11
OS version: 10.0.22631
Quartus Prime Information
Address bits: 64
Version: 24.2.0
Build: 40
Edition: Pro Edition
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Hello,
May I know if you are willing to share the design file with me so that I can try to replicate this Internal Error?
Thank you for your understanding.
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These are the design files, including the .vcd generated during the simulation, and a .vcd converted from a .wlf file.
This project is generated from HLS Compiler, which could be relevant. The issue appeared in the context of a larger project but I tested this logical "and" functionality to have as simple a test as possible.
The Quartus project is inside \luinv.prj\quartus
When generating the same project for a Cyclone V board in Quartus Lite, Power Analysis does work, which is why I think the problem might not be related to HLS Compiler.
Let me know if you have any updates or need more information.
Regards,
Noah
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Hi Noah,
Thank you so much for providing the design files. Let me try to look into your design first and update you back as soon as possible.
I appreciate your understanding.
Regards,
Aqid
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Hi Noah,
I can reproduce the internal error when running the Power Analyzer using the .vcd file you provided. I have escalated this issue to the internal team so they can investigate further.
I want to thank you for bringing this to our attention. I will update you on any information I get from them.
Regards,
Aqid
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Thank you as well for looking into this!
Do let me know if you have any updates.
Regards,
Noah
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Hi Noah,
So far, they had no chance to look into this yet, but one thing to confirm with you, how was this .vcd file was generated?
Also, is using other .vcd file having the same results so far from your findings?
Regards,
Aqid
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Hello again,
I tried two ways of generating it:
1) During the msim_run.tcl simulation script, by using the following code:
[...]
vcd file and_testbench.vcd
vcd add -r /*
run -all
vcd flush
[...]
2) Generating a .wlf file as is done by default in the msim_run.tcl generated by HLS Compiler, and then using the wlf2vcd tool in the Questasim command window. The .wlf file is set to be generated in the part of the code immediately preceding the code shown above:
[...]
set StdArithNoWarnings 1
set USER_DEFINED_ELAB_OPTIONS "+nowarnTFMPC -dpioutoftheblue 1 -sv_lib $fname_svlib -nodpiexports -wlf ../../vsim.wlf - voptargs=+acc"
elab
onfinish {stop}
quietly set StdArithNoWarnings 1
log -r *
[...]
Regards,
Noah
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Hi Noah,
Thank you for the information shared. The internal team will have someone take a look on this by this week.
I will share more if got any more updates.
Regadrs,
Aqid
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Hi Noah,
We have root caused the issue. A fix for this issue will be scheduled on the upcoming version.
As a workaround for this, please remove the following line from the QSF file and rerun the full flow:
set_instance_assignment -name PARTITION component_and_func -to "and_func:and_func_inst"
Thanks.
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