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Hi,
I initialized my ROM memory (instr_mem) by using the $readmemh task. The ROM was successfully complied and simulated, but the waveform show 32'hxxxxxxxx in instr_mem. It seems the 'instr_mem' didn't get the value from mem_instruction.txt file.
module mips_mem(addr1,data_in1,data_out1,we1,
addr2,data_in2,data_out2,we2,
rst_b,clk);
// Boundaries and lengths of each segment
// Note that '_top' addresses off by one; the actual top is one less
// than the values below.
// '_w' values are word addresses
input rst_b;
input clk;
// Inputs and ouptuts: Port 1
input [5:0] addr1; // Memory address
input [31:0] data_in1; // Memory write data
output [31:0] data_out1; // Memory read data
reg [31:0] data_out1;
input [0:3] we1; // Write enable (active high; 1 bit per byte)
// Inputs and outputs: Port 2
input [5:0] addr2; // Memory address
input [31:0] data_in2; // Memory write data
output [31:0] data_out2; // Memory read data
reg [31:0] data_out2;
input [0:3] we2; // Write enable (active high; 1 bit per byte)
o
// Memory segments
reg [31:0] data_mem[0:63];
reg [31:0] instr_mem[0:63];
// Verilog implementation stuff
integer i;
wire [31:0] write_mask1 = {we1[3], we1[3], we1[3], we1[3],
we1[3], we1[3], we1[3], we1[3],
we1[2], we1[2], we1[2], we1[2],
we1[2], we1[2], we1[2], we1[2],
we1[1], we1[1], we1[1], we1[1],
we1[1], we1[1], we1[1], we1[1],
we1[0], we1[0], we1[0], we1[0],
we1[0], we1[0], we1[0], we1[0]};
// Handle Port 1 Read
initial
begin
$readmemh("mem_instruction.txt", instr_mem);
end
always @(posedge clk or negedge rst_b) begin
if(rst_b==1'b0) begin
data_out1 <= 32'hxxxxxxxx;
end
else begin
data_out1 <=instr_mem[addr1];
end
end
endmodule
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You need to provide a lot more context.
What version of Quartus?
What simulator and version?
Show the contents (at least some lines, not all) of your memory init file.
In your waveform display, can you add other signals like addr1[5:0]?
BTW you can collapse the data bit display, no need to show individual bits.
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Quartus Prime # Version 20.1.1
mem_Instruction.txt
2402000a
24080005
2509012c
240a01f4
254b0022
256b002d
0000000c
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
The screenshot of waveform of addr1[5:0] signal
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I did the RTL simulation.
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Hi,
I printed out the content of mem_instr by using $display. The mem_instruction.txt seems successfully included in the design.
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What version of Quartus? Quartus Prime # Version 20.1.1
Show the contents (at least some lines, not all) of your memory init file.
2402000a
24080005
2509012c
240a01f4
254b0022
256b002d
0000000c
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
In your waveform display, can you add other signals like addr1[5:0]?
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Could you share the design .qar files and testbench so I can try to duplicate the issue from my side?
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Hi,
The mips_mem is the part of the MIPS processor design. The testbench was used to test hold processor,
// Top module for the MIPS processor core
// NOT synthesizable Verilog!
`timescale 1ns/100ps
module testbench;
reg [31:0] i;
reg [29:0] addr;
reg rst_b;
wire halted;
//parameter
parameter start = 0, halfPeriod = 50;
reg clk;
// The clock
initial
clk = start;
always
#halfPeriod clk = ~clk;
// The mips_top core
mips_top inst_mips(.clk(clk), .rst_b(rst_b), .halted(halted));
initial
begin
rst_b = 0;
#75;
rst_b <= 1;
end
always @(halted)
begin
#0;
if(halted === 1'b1)
$finish;
end
endmodule
Hi, I attached the design .qar file to this post.
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I am checking on your design. Will let you know if any finding.
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The $readmemh does work with Quartus. I suspecting design coding style.
Could you try to integrate the Quartus ROM template in your design?
Right click on any design file -> Insert template -> Verilog/VHDL -> RAMs and ROMs -> Dual Port ROM.
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Hi,
I have integrated a Quartus dual port ram template in my design. It still doesn't work. I used the RTL simulation to generate the waveform. The waveform of ram instantiation still shows 32'bxxxxxxxxxxxxxxxx.
I attached the design .qar file to this post.
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Any update/progress in this case? Do you need further help?
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.
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