How can I convert a Verilog code file into a BDF file

[fengtianwenming]

I'm currently using Quartus 18.0. I've successfully written Verilog files that compile and simulate without any issues. However, I'm now seeking to generate BDF files directly from these Verilog code files. This would allow me to view and modify the internal gate-level circuits, unlike the limited functionality offered by the RTL Viewer. Essentially, I'm looking for an editable and compilable BDF file, ideally without having to rebuild it from scratch. Your assistance on this matter would be greatly appreciated. Thank you!

[sstrell]

Only possible in Quartus Prime Standard edition.  File menu -> Create/Update.

[fengtianwenming]

Thank you for your response. It seems you've correctly interpreted that "Create symbol file for current file" might be used to generate a symbol file (BSF file) for the code file, enabling its integration into a schematic. However, the challenge I'm facing is that I'm seeking to convert Verilog code into a BDF file containing the internal gate-level circuitry. I want to manipulate and modify it directly, akin to the detailed circuits visible in the RTL Viewer. Do you have any suggestions or methods to accomplish this?

[sstrell]

No there’s no way to do that. In the long run, learning an HDL is going to be way more beneficial and time-saving vs manipulating a schematic.

[fengtianwenming]

Thank you for your response. I'm sad to hear about this fact.

[SyafieqS]

Long run HDL is good way, eventually BDF gonna EOL.

Let me know if there is any update on this

[SyafieqS]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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