How do I do line by line timing analysis in Quartus Prime Timing Analyzer?

[Pack_of_lone_wolves]

I am familiar with the following timing analysis flow:

1. Write an HDL design file (mostly .sv or .v). 
2. Simulate it.
3. Integrate it into the project.
4. Do synthesis, Fitter.
5. Open timing analyzer -> Setup Summary / Top failing paths.

When I do such things, I find that there is a negative setup slack at one of the registers which gets its value from FW, and this value comes from a different clock domain (clocked by a different clock at different frequency). This register is only updated when FW runs some script periodically.

The output of this register goes further down to logic which has several combinational and Boolean operators expressed as a conditional statement, which indicates that the logic down the line is going to consume more resources.

If I sort the timing analyzer view by the delay at each level, I see that some of the conditional blocks as above are having more delay but they also have a positive slack. I am curious that if I simplify those expressions to have less logic, will this compensate the negative slack on the register from which these blocks get their input?

What I see is that, the timing analyzer has a number of launch and latch nodes, which I can locate in the design file. What I want is that I have design file, I want to select a specific signal (reg/wire) as a node and I want to know the gate delay of any expression, for ex:

assign output = ((count_1 >= (reg_1 + 1)) && (count_2 <= (reg_2 - 2)));

All of the LHS signals are either regs or wires driven by regs. This expression will have outputs of two comparators ANDed together, so I want to know the combinational delay from the (reg_1 + 1) till the output, so that I can do some adjustments/tweaking/optimization or divide this logic into multiple registered levels.

I want to go from variables -> nodes -> delays. Currently it is: Failed path -> Nodes (with delays) -> variables (locate in design file).

[sstrell]

Finding paths in the timing analyzer doesn't really work like that.  All timing paths are register (or input) to register (or output).  As such, you'd want to look for the timing paths between the sources of those signals and the output port or register.  The Data Arrival timing section of a report generated from "Report Timing" with the full detail option selected breaks down the incremental delays through combinational logic, which sounds like what you are looking for.

You could also open the RTL Viewer or Technology Map Viewer, find the paths you want to analyze, and right-click them to cross-probe to the timing analyzer and generate the reports for the paths you need.

[Pack_of_lone_wolves]

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@sstrell wrote:

You could also open the RTL Viewer or Technology Map Viewer, find the paths you want to analyze, and right-click them to cross-probe to the timing analyzer and generate the reports for the paths you need.

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I'd exactly want to do that, let me try and confirm if I'm able to do this exact thing. (I regret my late reply)

[SyafieqS]

Let me know if there is any update from previous reply

[SyafieqS]

Let me know if you are able to cross probe node in rtl viewer.

This should be pretty straight forward.

[Pack_of_lone_wolves]

If I open the timing analyzer, I can select a node/path and then I can cross probe it in the RTL/Technology map viewer. But, I cannot select a node/path in RTL/Tech Map viewer, right click to see that path in timing analyzer.

[RichardTanSY_Intel]

You can't right click a node in the RTL viewer and locate back to the failing path in the Timing Analyzer.

All the options available can be seen when you right click > Locate node.

Regards,

Richard Tan

[Pack_of_lone_wolves]

I do not want to locate back to the failing path. I am aware of the available options visible once the right click > locate node is done.

What I want is to select any path and I want to see the overall combinational delay through the path b/w any two nodes (irrespective of the path is failing or not), (the nodes could be two or more FFs or Adaptive LUTs or Adaptive LMs), so that I can tweak the HDL code and compare the changes in the delay values before and after change.

I am aware that some delay values can be seen in Chip Planner. But I have always found those delay values once I select a path / a node in Timing Analyzer and do the locate node in Chip Planner.

Getting delay values from RTL/Tech Map viewer on any path whatsoever will help in making more timing aware design changes which expedite the overall design cycle. 

[SyafieqS · Accepted solution]

I understood your intention however I don't think Quartus able to do that. In Quartus failing path only shown in STA report as it is, If you need the path b/w of the failing, (seem like a chain path of that node). you probably need to manually report timing (playing with from/to of intention node to manually compare it which I think bit tedious).

Let me know if there is any concern.

[SyafieqS]

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