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How to fix setup violation for signal tap?

Chris039
Novice
941 Views

Hi,

 

How to fix the setup violation for the signals below? clk is the clock signal that I set in the signal tap.

 

Chris039_0-1708500687766.png

Chris039_1-1708500741228.png

 

 

Thanks

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13 Replies
Chris039
Novice
928 Views
What are the timing constraints we need to add in the design when we use signal tap ?
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RichardTanSY_Intel
838 Views

We do not write constraint directly to the signal tap. The Signal tap is bound by the same sdc constraints used for the rest of the design.

The following techniques can help you preserve timing in designs that include the Signal Tap logic analyzer:


-Avoid adding critical path signals to the .stp file.

-Minimize the number of combinational signals you add to the .stp file, and add registers whenever possible.

-Specify an fMAX constraint for each clock in the design.


Reference: https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/timing-preservation.html


"clk is the clock signal that I set in the signal tap."

>>Do your design only have one clock or multiple clock signal?

There is a possibility that you might using wrong clock to sampling some of the signals,


Regards,

Richard Tan


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Chris039
Novice
786 Views

Hi Richard,

 

 

The suggestion does not help for this scenario. The timing violation occurs between the clk to the signal tap signal. How to resolve this? It is a clock to signal tap timing path violation, not between the logic in the core design.

 

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RichardTanSY_Intel
779 Views

Kindly share your design by archiving the project (Project > Archive Project) so that I can investigate it further.
What is the Quartus version and the edition (pro/std) used? 

If the design cannot be shared publicly, please let me know, and I'll send you an email to facilitate the transfer of files through FTP(Files Transfer Protocol).

Regards,

Richard Tan

 

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RichardTanSY_Intel
755 Views

Hi,


Do you able to share your design?


Regards,

Richard Tan


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Chris039
Novice
743 Views

Hi Richard,

 

I cannot share the design for confidential information. I tried to create a simple design but the timing violation does not occur in the simple design. The timing violation occur from the input clock port to the signal tap data signal, what we can try to fix this?

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RichardTanSY_Intel
717 Views

It will be challenging to debug without the design. Here are some debugging steps that we can try to isolate the issue.

 

-What is the clock frequency that you are using?

Could you check the following when specifying the acquisition clock:

https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/specifying-the-clock-sample-depth-and.html#mwh1410384497703__section_lr4_qrj_nmb

 

-Is your design uses a lot of resources? Perhaps try to reduce the numbers of signal tapped to check or reduce the sample depth.

Perhaps isolate the impacted module and try to add signal tap to see if the same timing path still fail.

 

-Try to add pipeline factor (maximum 5)

https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/specifying-pipeline-settings.html

 

Could you share screenshot of the failed timing path's "Data Arrival Path" in the "Data Path" and the "Statistic" Report in the Timing Analyzer?
What is the number of logic levels? 

RichardTanSY_Intel_0-1709191431322.png

 

Regards,

Richard Tan

 

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RichardTanSY_Intel
677 Views

Dropping a note to ask if my last reply was helpful to you?

Do you able to resolve the issue? 

 

Regards,

Richard Tan

 

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Chris039
Novice
670 Views

Please let me check the suggestion and I will get back to you.

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Chris039
Novice
660 Views

Hi Richard,

The timing violation is actually a hold but not setup. I apologies for the mistake about the setup violation

-Try to add pipeline factor (maximum 5)
It is a clock input signal and not the real data signal. I am not sure can add the pipeline to clock signal or not

 

Could you share screenshot of the failed timing path's "Data Arrival Path" in the "Data Path" and the "Statistic" Report in the Timing Analyzer?
What is the number of logic levels? 

Chris039_2-1709551761562.png

 

Chris039_1-1709551681628.png

 

 

 

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RichardTanSY_Intel
574 Views

1. Check that Assignments -> Settings -> Fitter has Optimize Hold Timing set to All Paths and Optimize Multi-Corner is checked. This tells the router to add delays to try and meet hold requirements. 


2. Have you try to reduce the numbers of signal tapped to check or reduce the sample depth?


3. Given that the design cannot be shared, could we obtain the Database (DB) archive from you? Please note that this won't include any RTL files.

 Security Note: A database-only archive does not guarantee protection for sharing your design without sharing your RTL. The RTL Netlist Viewer, Technology Map Viewer, and other views, along with the EDA Netlist Writer, are still available for projects exported using this feature.

You may check this on how to create a DB: 

https://www.intel.com/content/www/us/en/docs/programmable/683463/current/creating-database-only-archives.html

p/s: If the design cannot be shared publicly, please let me know, and I'll send you an email to facilitate the transfer of files through FTP(Files Transfer Protocol).


Regards,

Richard Tan


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RichardTanSY_Intel
487 Views

Hi,


Do you have any update on this ?


Regards,

Richard Tan


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RichardTanSY_Intel
428 Views

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support.

We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to let us know. 

Thank you for reaching out to us!


Best Regards,

Richard Tan


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