How to set Timing Constraints (Tco, Tsu, Fast Output Register)

Altera_Forum · ‎08-04-2011

Hi, I'm trying to include "Flash Altera IP University Program Core" into my project.

I read in this Altera tutorial (ftp:// ftp.altera.com/up/pub/Altera_Material/11.0/University_Program_IP_Cores/Memory/Flash_Memory_IP_Core.pdf) that

 the timing constraints for the F L_¤ signals should be set as follows:
1. Fast Output Register &#64258;ag should be turned ON
2. Tco requirement should be set to no more than 10ns, and
3. Tsu requirement should be set to no more than 10ns.

Could somebody tell me a step by step procedure to do these 3 setting?

Altera_Forum · ‎08-04-2011

for classic timing you enter tSU/tH/tCO directly

for timequest you may find this thread useful

http://www.alteraforum.com/forum/showthread.php?p=125824#post125824

Altera_Forum · ‎08-05-2011

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for classic timing you enter tSU/tH/tCO directly

for timequest you may find this thread useful

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Could you tell me a step by step procedure to do these 3 setting?