How to turn off the optimization that removes repeated logic?

[Altera_Forum]

Hi, 

 I'm creating a small program using a block diagram. I want a propagation delay on a certain signal, so i've put in 2 not gates for this propagation delay. How do i disable the optimization in Quartus to stop it removing these two not gates within a block diagram? I know how to do it in verilog but i need to know how to do it with a block diagram.  I've attempted to go in to the Assignment Editor, selecting the logic elements in the 'To' cell, and choosing 'Netlist Optimazations' in the 'Assignment Name', with a 'Value' of 'Never Allow' and for it to enable this assignment. I've also attempted the same with 'Perform Physical Synthesis for Combinational Logic for Performance' with a 'Value' of 'Off'. But when i look in the RTL viewer, the not gates have been removed.  Any help is much appreciated.

[Altera_Forum]

You can use the LCELL primitive, these won't be removed by optimization. 

Note that the control you have over those delays is poor. It's subject to placement, process, voltage and temperature variations. Depending on what you need, using the programmable  delays on the output elements might work better.  Also, do you really need those delays?

[Altera_Forum]

You'll find a many previous threads discussing logic cell delay, e.g.: 

http://www.alteraforum.com/forum/showthread.php?t=2418 http://www.alteraforum.com/forum/showthread.php?t=3068

[Altera_Forum]

--- Quote Start ---  You can use the LCELL primitive, these won't be removed by optimization. Note that the control you have over those delays is poor. It's subject to placement, process, voltage and temperature variations. Depending on what you need, using the programmable  delays on the output elements might work better.  Also, do you really need those delays?  --- Quote End ---    I found this whilst googling but isn't the LCELL primitive turned off by default now? Or that is what it appeared to be when i found the option in the software.

[Altera_Forum]

You can use the synthesis attribute "Keep Combinational Node/Implement as Output of Logic Cell", this is described on page 16-42 of the 12.1 version of the Quartus Handbook. For verilog, you declare your wire of the node you want to not be synthesized away like this: 

 wire notout1 /* synthesis keep = 1 */; assign notout = notin;  Now this instructs the synthesis not to remove the notout1 node, but if it can lump it into the same LUT that implements notin, it may do that, so you may need to declare notin the same way. As people stated before, the delay's are poorly controlled. I've spent some time trying to shove extra gates in for delay to fix timing violations and it never really helped in the end. If you describe why you're doing this there may be a better solution.

[Altera_Forum]

Added gates or LCELLS to a path is never reliable as it can be highly affected by temperature and routing every time you recomile it. I suggest, like the poster above, you find an alternative.

[Altera_Forum]

(On a PM, the original poster told me he just wants to use the delay to create cases where he illustrates the need for timing analysis, so it should suffice for his needes)