Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16875 Discussions

I got error because of not proper use of std_logic and bit, please help me in solving

Altera_Forum
Honored Contributor II
2,392 Views

---------------------------------------------------------------------------------- 

-- Company:  

-- Engineer:  

--  

-- Create Date: 15:16:54 02/14/2011  

-- Design Name:  

-- Module Name: glu - Behavioral  

-- Project Name:  

-- Target Devices:  

-- Tool versions:  

-- Description:  

-- 

-- Dependencies:  

-- 

-- Revision:  

-- Revision 0.01 - File Created 

-- Additional Comments:  

-- 

---------------------------------------------------------------------------------- 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.STD_LOGIC_ARITH.ALL; 

use IEEE.STD_LOGIC_UNSIGNED.ALL; 

 

---- Uncomment the following library declaration if instantiating 

---- any Xilinx primitives in this code. 

--library UNISIM; 

--use UNISIM.VComponents.all; 

 

---------------------------------------------------------------------------------- 

 

--ENTITY Declarations 

---------------------------------------------------------------------------------- 

ENTITY glu is 

 

port(  

 

Data_reg: OUT STD_LOGIC_vector(11 downto 0); 

 

Creg: out STD_LOGIC_vector(4 downto 0)); 

 

end glu; 

 

---------------------------------------------------------------------------------- 

--Architecture Body 

 

---------------------------------------------------------------------------------- 

 

architecture Behavioral of glu is 

 

TYPE Memory IS ARRAY (0 TO 1026) OF STD_LOGIC_VECTOR(7 DOWNTO 0); 

 

SIGNAL Ram : Memory; 

rows and 8 bit in each rowSIGNAL Temp1,Temp2,Temp3: STD_LOGIC_VECTOR(15 DOWNTO 0) ;  

SIGNAL A1A0,CS: STD_LOGIC_VECTOR(1 DOWNTO 0) ;  

SIGNAL Temp2,Mirror_Num10 ,Mirror_Num20,Axis10,Temp10,Temp40,Temp3:STD_LOGIC_VECTOR(15 DOWNTO 0); 

SIGNAL Temp1,Mirror_Num ,Mirror_Num2 ,Temp4,Axis : BIT_VECTOR(15 DOWNTO 0); 

 

SIGNAL Cur_Add: STD_LOGIC_VECTOR(31 downto 0); 

 

SIGNAL Base_Add:STD_LOGIC_VECTOR:=x"00000000";  

 

SIGNAL Mnum_Add:STD_LOGIC_VECTOR:=x"00000403"; 

 

SIGNAL flag:STD_LOGIC_VECTOR:= x"00000400"; 

 

SIGNAL Axis_Add:STD_LOGIC_VECTOR:=x"00000401"; 

 

 

 

SIGNAL X:STD_LOGIC_VECTOR:="000000000000000"; 

SIGNAL Y :STD_LOGIC_VECTOR:="0000000000000010"; 

 

 

BEGIN 

 

process(Ram(Conv_Integer(flag))) -- Process begin and we take the flag in sensitivity list. 

 

BEGIN 

 

IF ( Ram(Conv_Integer(flag))='1') THEN  

 

Mirror_Num(15 DOWNTO 8) <= CONV_STD_LOGIC_VECTOR (Ram(Conv_Integer(Mnum_Add)));  

--Store the value of the mirror number in the Temp1 

Mirror_Num(7 DOWNTO 0) <= CONV_STD_LOGIC_VECTOR (Ram(Conv_Integer(Mnum_Add+1)));  

 

Axis(15 DOWNTO 8) <= CONV_STD_LOGIC_VECTOR (Ram(Conv_Integer(Axis_Add)));  

--Store the value for choosing X or Y axis in temp2  

Axis(7 DOWNTO 0) <= CONV_STD_LOGIC_VECTOR (Ram(Conv_Integer(Axis_Add+1)));  

 

Mirror_Num2 <= Mirror_Num sla 1 ; --Multiply mirror number by 2 

 

If(Axis=X) THEN --Check for the X axis 

 

 

 

 

Cur_Add<= (Base_Add + (Mirror_Num sla 2) + Axis); --If we have to move the mirror in X axis then current address of BRAM is 

 

Temp1 <= Mirror_Num2 + Axis ; 

 

ELSIf(Axis=Y) THEN --Check for the Y axis 

 

 

Cur_Add<= (Base_Add + (Mirror_Num sla 2) + Axis); --If we have to move the mirror in X axis then current address of BRAM is 

 

Temp1 <= Axis sra 1 + Mirror_Num2; 

 

END IF; 

Temp4 <= Temp1 sra 2; 

 

Mirror_Num10 <= CONV_STD_LOGIC_VECTOR( Mirror_Num) ; 

Mirror_Num20 <= CONV_STD_LOGIC_VECTOR ( Mirror_Num2 ) ; 

Axis10 <= CONV_STD_LOGIC_VECTOR ( Axis ) ; 

Temp10 <= CONV_STD_LOGIC_VECTOR ( Temp1 ) ; 

Temp40 <= CONV_STD_LOGIC_VECTOR ( Temp4 ) ; 

 

DATA_reg(11:8)<=Ram(Conv_Integer(Cur_Add))(3:0); -- Put the value of the current address of BRAM to Data reg 

 

DATA_reg(7:0)<=Ram(Conv_Integer(Cur_Add+1)); 

 

Temp2 <= conv_STD_LOGIC_vector((conv_integer(Temp1) mod 4),16); --Calculation for the Position in Particular DAC according to mirrir number and axis selection. 

 

A1A0 <= Temp2(1 DOWNTO 0); 

 

Temp3 <= conv_STD_LOGIC_vector(conv_integer(Temp4),16) ;  

 

IF(Temp3="0000000000000000") THEN 

CS<="01"; 

 

ELSIF(Temp3="0000000000000001") THEN 

CS<="10"; 

 

END IF; 

--Calculation for chip select 

 

CS <= Temp3(1 DOWNTO 0); 

 

Creg(4 DOWNTO 3) <= CS ; -- Put the value for chip select and A1A0 in the control registor. 

 

Creg(2 DOWNTO 1) <= A1A0 ;  

 

Creg(0) <= '0' ; -- set the value of lsb of control registor to 0 for R/(W)bar 

 

-- If flag=0 then exit. 

 

 

 

END IF; 

 

END PROCESS; 

 

Creg(4 DOWNTO 3) <= "11" ;  

flag <= 0;  

END Behavioral; 

 

-------------------------------------------------------------------------------
0 Kudos
9 Replies
Altera_Forum
Honored Contributor II
913 Views

a std_logic_vector is not a bit vector. 

 

Why not just declare Temp1,Mirror_Num ,Mirror_Num2 ,Temp4,Axis as std_logic_vectors?
0 Kudos
Altera_Forum
Honored Contributor II
913 Views

because of sla and sra does not support std_logic_vector

0 Kudos
Altera_Forum
Honored Contributor II
913 Views

You might want to try using the numeric_std package. That has signed and unsigned types that support sla and sra, and you can convert them to std_logic_vector.

0 Kudos
Altera_Forum
Honored Contributor II
913 Views

Actually can u tell me the instruction for converting std_logic_vector to bit_vector. 

 

And from integer to bit_vector and vice versa.
0 Kudos
Altera_Forum
Honored Contributor II
913 Views

You can just use the to_stdlogicvector/to_stdlogic/to_bitvector/to_bit functions in the std_logic_1164 library. 

 

The numeric_std library has sra and sla functions for unsigned and signed types, that you can convert to and from integer. 

 

signal s : signed(7 downto 0); 

 

.... 

s <= s sra 5; 

i <= to_integer(s);
0 Kudos
Altera_Forum
Honored Contributor II
913 Views

I use this , 

 

signal s : signed(7 downto 0); 

 

.... 

mul<= mul sra 5; 

temp<= to_integer(mul); 

 

 

but this gives me error defination of operator match here
0 Kudos
Altera_Forum
Honored Contributor II
913 Views

have you included the numeric_std library and deleted the std_logic_arith library?

0 Kudos
Altera_Forum
Honored Contributor II
913 Views

I use these library 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.STD_LOGIC_ARITH.ALL; 

 

use IEEE.numeric_std.all;
0 Kudos
Altera_Forum
Honored Contributor II
913 Views

The std_logic_arith library defines its own signed and unsigned types, but does not include sra and srl functions. It is also NOT an IEEE standard library (neither is std_logic_signed/unsigned) 

 

numeric_std defines its own signed/unsigned types and also includes sra/srl functions, and it IS the IEEE standard library. Using numeric_std and std_logic_arith in the same file causes conflicts that will cause neither of them to work (unless you reference everything specifically). 

 

The answer is to delete std_logic_arith.
0 Kudos
Reply