hidden text to trigger early load of fonts ПродукцияПродукцияПродукцияПродукция Các sản phẩmCác sản phẩmCác sản phẩmCác sản phẩm المنتجاتالمنتجاتالمنتجاتالمنتجات מוצריםמוצריםמוצריםמוצרים
Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17039 Discussions

Is it possible to implement AES-256 algorithm in Altera cyclone iv E DE2 115 board?

Altera_Forum
Honored Contributor II
1,493 Views

Hi guys, 

 

If its not possible to implement in this board, please suggest me any board?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
718 Views

Have a look at "fpga implementation of aes encryption and decryption (http://www.design-reuse.com/articles/13981/fpga-implementation-of-aes-encryption-and-decryption.html)". Having a look at the 'Device utilization summary' I'd suggest you should be able to implement this in the DE2-115's FPGA. 

 

Also see "aes encrypter/decrypter (http://people.ece.cornell.edu/land/courses/ece5760/finalprojects/s2015/ar856/ece5760webpage/ece5760%20webpage/webpage_files.html)", which uses a DE2-115. 

 

Cheers, 

Alex
0 Kudos
Reply