Issue with TSE ip after quartus prime upgrade 22.4.0 build 94

[Antonino88x]

Hi,

I have updated Quartus from version 20.2 pro to the new 22.4.0 build 94. 

After manually updating all ip components, I see an issue on my design using tse version 21.0.0. These are the ip configurations:

Core variation: 10/100/1000Mb Eth MAC with 1000BASE-X/SGMII PCS

Internal fifo : enabled (2048 x 8bits both  rx and tx)

Number of ports: 1

Transceiver type :GXB

Mac option: only include statistics counters.

Device : Cyclone 10GX.

The issue seems on rx part of the mac. Analyzing internal signals with signal taps with rx_clk (internal clock), on gmii_rx_d bus I see on every rx packet that the preamble duration can change from 6 to 7 clock cycles. Every time the mac module receives a preamble with 6 clock duration it discards the packet (ff_rx_dsav is 0 and never rise).

Trying the same design with quartus  pro 20.2 and tse ip version 19.4.0, I see the same preamble variation but the mac ip always detects all rx packets as corrects.

These are my register configurations:

pcs status: 0x0000008D

pcs control:0x00000160

pcs if_mode:0x00000008

mac cmd config:0x0100013B

Can you please help me or have you already encountered a similar issue?

Thank you,

Antonino

[ZiYing_Intel]

Hi,

Thanks for submitting the issue.

Can share the .qar file? So that I can try debug the issue from my side.

Best regards,

Zi Ying

[ZiYing_Intel]

Hi,

For further information about preamble, please do refer link below, https://www.intel.com/content/www/us/en/support/programmable/articles/000083600.html

Best regards,

Zi Ying

[Antonino88x]

Hi Zi Ying,

sorry if I reply late but I can't share my project (forbidden by our company). 

From your link is clear than the receiver pcs may generates preamble with 6 octets.

My question is why in this case the new version of mac ip discards the received packet?