Manual routing in Quarutus

[dj-park]

I know there were similar questions in the forum, just want to double check with the most recent Quartus version. I am using Quartus Prime Pro 23.1 on Ubuntu 20.04.

Can I manually route so that it doesn't use routing resources in the specific regions?

Or at minimum, can I manually route so that it doesn't cross the specific region and fix it?

Xilinx Vivado does not have this feature but does have manual placement and routing (https://docs.xilinx.com/r/en-US/ug904-vivado-implementation/Manual-Routing).

I wonder if I can achieve this in Quartus.

[RichardTanSY_Intel]

You can use the Logic Lock feature in the Quartus in achieving specific placement and routing goals for your design. Logic Lock allows you to lock down the placement of certain logic elements (such as flip-flops, logic cells, or specific modules) to specific locations on the FPGA device.

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683641/current/defining-regions.html

However, it's important to note that the excessive use of Logic Lock regions may limit the flexibility of the Quartus tool to place & route the logic and could potentially lead to decreased performance or congestion issues. Therefore, it is recommended to use Logic Lock judiciously and analyze the impact on the overall design.

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

[dj-park]

Thanks for the reply. I am aware of Logic Lock region.
But I am asking about the fine-grain control over the routing. For example, with Logic Lock region, I don't have a control
over the nets that come in/out from the Logic Lock region. I want to control these nets so that they do not route over specific regions.

[sstrell]

You can set up routing regions that are associated with Logic Lock regions to do this.  This is normally used in the partial reconfiguration design flow since it's like you are removing part of the design while it's running and the rest of the design can continue running.  Look up routing regions and partial reconfiguration for details on this.

[dj-park]

Yes, I am aware of routing region as well. However, as mentioned in the reply above, the routing region does not have a control over the "interface nets." (the nets that come in/out from the logic lock region)

I want to control these nets so that they do not route over specific regions. My idea was to manually move over these nets if they end up routing over the regions. Thus, I asked the question whether we can manually route specific nets.

[RichardTanSY_Intel]

I have consulted with the engineering team regarding your request for fine-grained control over routing in Quartus. Unfortunately, the ability to specify exact routes to individual wires is not exposed to the public as it requires a deep understanding of the device and routing fabric.

However, you can utilize the RESERVE_ROUTE_REGION feature, which allows you to prevent other nets from mixing into a specified region. While this feature is not mandatory, it is commonly used in Partial Reconfiguration (PR) designs.

If you have any further questions or need additional assistance, please feel free to let me know.

Best Regards,

Richard Tan

[RichardTanSY_Intel]

I believe that your question has been addressed. Now, I will transition this thread to community support.

If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.