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15555 Discussions

Modelsim Simulator Error & Request about solutions and source files

Junmo
Beginner
375 Views

I have a two questions.

First,

I use the quartus 18.1 version and run gate level simulation using VWF.

I can see the simulation waveform result  but in this waveform the delay isn't considered. The output signal has  a 0ns delay. 

During simulation log,

The "Error: can't read "FileWatch(filename)": no such element in array" message was shown.

What does this message mean? Can it occur the 0ns delay problem?

 

Second,

I requested the solutions and source files about lab in this page (Solution Request for Intel® FPGA Academic Program) about 10 days ago.

 

But I didn't get any response.

 

Next semester, I will teach the subject using  Intel FPGA training kit which

has the Cyclone II and V.

 

I need the solutions and source files about courses ASAP.

 

Thanks.

 

 

0 Kudos
14 Replies
hareesh
Employee
346 Views

Hi Junmo,

Can you please share your simulation file.

 

Thanks,

 

 

Junmo
Beginner
340 Views

Hi.

 

This is a waveform.

The circuit is very simple(Full Adder).  The inputs are a, b, cin.

Output s is sum output. But it appears 0 ns delay.simulation waveform.jpg

hareesh
Employee
310 Views

Hi @Junmo,

i think this is a vwf limitation. I would recommend the users to use the questasim. for Questasim reference video link sharing here.

 

https://www.youtube.com/watch?v=60-beTWcJSM 

 

Junmo
Beginner
289 Views

Thanks for your response. I will try it.

hareesh
Employee
287 Views

Hi

APAS files access issue requested to IT team from my side. did get any id number or requested  mail id to identify you request.

Thanks,

Junmo
Beginner
282 Views

Thanks for your response.

 

My mail addr. is jmjung@kunsan.ac.kr.

 

Thanks.

hareesh
Employee
267 Views

Hi 

I sharing customer support for ASAP issue. pls contact there.

 if you don't have any another quire i'll close the case. pls conform me.

https://it.intel.com/#/topic/5457

 

Thanks,

Junmo
Beginner
263 Views

I can't access that link. Is that right?

Would you mind checking that link?

 

And, I got the solutions today morning. But I couldn't solve 0ns delay on Gate level simulation in VWF.

 

Thanks.

hareesh
Employee
256 Views

Hi 

Did you tried in Modelsim?

Junmo
Beginner
251 Views

Yes.

 

I runned the Gate level simulaion  on Quartus II 18.1 version using VWF university program.

 

 

hareesh
Employee
217 Views

Hi @Junmo ,

I think in your design you are not using CLK. for reference i am sharing full adder VHDL code(i am not good in Verilog HDL, so i sharing VHDL) and simulation output files. Go through bellow attached files. 

 

Thanks, 

 

hareesh
Employee
198 Views

Hi,

I think you got solution for your issue. if you don't have any quires I'll close the case. pls respond.


Thanks,


Junmo
Beginner
193 Views

Ok.

 

Thanks for your help. 

hareesh
Employee
184 Views

Hi,

 

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

 

Thanks,

 

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