I have a two questions.
I use the quartus 18.1 version and run gate level simulation using VWF.
I can see the simulation waveform result but in this waveform the delay isn't considered. The output signal has a 0ns delay.
During simulation log,
The "Error: can't read "FileWatch(filename)": no such element in array" message was shown.
What does this message mean? Can it occur the 0ns delay problem?
I requested the solutions and source files about lab in this page (Solution Request for Intel® FPGA Academic Program) about 10 days ago.
But I didn't get any response.
Next semester, I will teach the subject using Intel FPGA training kit which
has the Cyclone II and V.
I need the solutions and source files about courses ASAP.