My device is a Macbook Pro 14' with an M1 chip. I have installed Parallels Desktop 18 for Mac Standard Edition (version 18.2.0) on my computer. I have also created a 64-bit ARM version of Windows 11 (22H2) and successfully installed Quartus Prime Lite Edition (22.1std.0.915) on it.
I can successfully open Quartus II and perform tasks like creating projects and compiling. However, I am unable to run simulations. It works on other computers, but here I only get an error message.
As an example, let's consider a simple half adder. The following error message appears when trying to run the simulation:
Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/22.1std/questa_fse/win64/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off adder_sub_4bit -c adder_sub_4bit --vector_source="E:/wednesday_class/adder_sub_4bit/Waveform1.vwf" --testbench_file="E:/wednesday_class/adder_sub_4bit/simulation/qsim/Waveform1.vwf.vt"
TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function free
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Info: Copyright (C) 2022 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sun May 28 11:22:10 2023
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off adder_sub_4bit -c adder_sub_4bit --vector_source=E:/wednesday_class/adder_sub_4bit/Waveform1.vwf --testbench_file=E:/wednesday_class/adder_sub_4bit/simulation/qsim/Waveform1.vwf.vt
Info (119006): Selected device 10M50DAF484C7G for design "adder_sub_4bit"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="E:/wednesday_class/adder_sub_4bit/simulation/qsim/" adder_sub_4bit -c adder_sub_4bit
TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function free
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Info: Copyright (C) 2022 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sun May 28 11:22:11 2023
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=E:/wednesday_class/adder_sub_4bit/simulation/qsim/ adder_sub_4bit -c adder_sub_4bit
Info (119006): Selected device 10M50DAF484C7G for design "adder_sub_4bit"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file adder_sub_4bit.vo in folder "E:/wednesday_class/adder_sub_4bit/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13067 megabytes
Info: Processing ended: Sun May 28 11:22:12 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
E:/wednesday_class/adder_sub_4bit/simulation/qsim/adder_sub_4bit.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/intelfpga_lite/22.1std/questa_fse/win64//vsim -c -do adder_sub_4bit.do
Error.
1 Solution
Link Copied
