Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15388 Discussions

Modelsim "Types do not match"

Altera_Forum
Honored Contributor II
2,599 Views

Hi, I've wrote VHDL code, and also a testbench. Its my first attempt writing testbench so go easy please. I think it's correct but Modelsim keeps giving errors; I have tried numerous times with no joy.  

 

This is top level: 

 

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity quarter_round is generic(l:integer:=9); port(y : in unsigned(127 downto 0); z : out unsigned( 127 downto 0) ); end quarter_round; Architecture quarter_round_arch of quarter_round is component rtleft is generic(l:integer); port( a: in unsigned( 31 downto 0); b: out unsigned( 31 downto 0)); end component; signal y0 : unsigned( 31 downto 0); signal y1 : unsigned( 31 downto 0); signal y2 : unsigned( 31 downto 0); signal y3 : unsigned( 31 downto 0); signal i1,i2,i3,i4 :unsigned( 31 downto 0); signal j1,j2,j3,j4 :unsigned( 31 downto 0); signal z0,z1,z2,z3 :unsigned( 31 downto 0); begin y0 <=y(127 downto 96); y1 <=y(95 downto 64); y2 <=y(63 downto 32); y3 <=y(31 downto 0); i1<=y0+y3; r1:rtleft generic map(7) port map(i1,j1); z1<=j1 xor y1; i2<=z1+y0; r2:rtleft generic map(9) port map(i2,j2); z2<=j2 xor y2; i3<=z2+z1; r3:rtleft generic map(13) port map(i3,j3); z3<=j3 xor y3; i4<=z3+z2; r4:rtleft generic map(18) port map(i4,j4); z0<=j4 xor y0; z<=z0&z1&z2&z3; end quarter_round_arch; 

 

Component 'rtleft' : 

 

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rtleft is generic (l:integer:=7); port( a: in unsigned( 31 downto 0); b: out unsigned( 31 downto 0)); end rtleft; architecture dataflow of rtleft is begin b<=a(31-l downto 0)& a(31 downto 31-l+1); end dataflow; 

 

And the failing testbench: 

 

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY quarter_round_vhd_tst IS END quarter_round_vhd_tst; ARCHITECTURE test of quarter_round_vhd_tst IS COMPONENT quarter_round PORT ( y : IN STD_LOGIC_VECTOR(127 DOWNTO 0); z : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) ); END COMPONENT; SIGNAL clk : bit := '0'; SIGNAL reset : bit := '0'; SIGNAL y : STD_LOGIC_VECTOR(127 DOWNTO 0); SIGNAL z : STD_LOGIC_VECTOR(127 DOWNTO 0); BEGIN DUT : quarter_round PORT MAP ( y => y, z => z ); y <= x"201f1e1d1c1b1a191817161514131211"; PROCESS BEGIN clk <= '0' ; wait for 10 ns; z <= y ; clk <= '1'; wait for 10 ns; END PROCESS; END test;  

 

The error in modelsim " Types do not match between component and entity for port "y". 

Again, I think the testbench is correct. Looking to input a 128 bit value for y and view the result (of z) on the wave. 

Thanks
0 Kudos
8 Replies
Altera_Forum
Honored Contributor II
543 Views

hi. 

 

In entity quarter_round you declared port y as unsigned. When you declared the component in the testbench, you declared the port as std_logic_vector. Usually the entity ports are of type std_logic or std_logic_vector.
Altera_Forum
Honored Contributor II
543 Views

Hi, 

thanks for your reply. I edited the entity quarterround and Modelsim allows me to simulate. I changed all to unsigned 

 

It compiles in Modelsim by no output for z.
Altera_Forum
Honored Contributor II
543 Views

What is ModelSim showing? Is z in 'U' state?

Altera_Forum
Honored Contributor II
543 Views

https://www.alteraforum.com/forum/attachment.php?attachmentid=8866  

 

 

I have made progress, output still incorrect though....
Altera_Forum
Honored Contributor II
543 Views

Please, post the entire quartus project ( zipped ). May be I give a better answer.

Altera_Forum
Honored Contributor II
543 Views

Thanks, thats it. 

 

The modelsim tb file is .vht, in simulation.
Altera_Forum
Honored Contributor II
543 Views

Nothing like a good testbench...

Altera_Forum
Honored Contributor II
543 Views

Thanks! I'll try it out now

Reply