Modifying PRBS Frequency in Stratix V

[DeadEnd]

Hello! I have a question while reviewing the approach to validating Bit Error Rate using PRBS with Stratix V.

The purpose of my inquiry is to change the frequency of the transmitted data, and I need clarification on modifications required in the existing code written by the previous developer.

In the first code, the .sdc file specifies a clock frequency of 644.53125MHz through the C64453mhz variable.

In the second code, the refclk_in_clk of the low_latency_10G_1ch module in the .v file is configured to operate with the previously specified C64453mhz.

If I want to change the frequency, is it sufficient to modify the value of the C64453mhz variable in the .sdc file and then compile?

Will there be any issues if I set the frequency to 6GHz or similar? Alternatively, are there specific allowable values for this variable?

Please provide additional code or information if necessary.

============== Coding ==============

.sdc

create_clock -period 100MHz [get_ports {C100mhz}]
create_clock -period 644.53125MHz [get_ports {C64453mhz}]
create_clock -name {altera_reserved_tck} -period 100 [get_ports {altera_reserved_tck}]
create_clock -period 100MHz [get_keepers {*alt_xcvr_reconfig_dfe_sv:dfe_sv|alt_xcvr_reconfig_dfe_cal_sv:inst_xreconfig_cal|dfe_calibrator_sv:inst_calibrator*|alt_cal_edge_detect:inst_edge_detect|alt_edge_det_ff1}]
derive_pll_clocks -create_base_clocks

.v

module gx_link_test_example (

input wire C64453mhz,
input wire C100mhz,

input  wire GXB_RXL11,
output wire GXB_TXL11
);

wire tx_ready;
wire rx_ready;
wire pll_locked;
wire reconfig_busy;

   wire [7:0]    system_reset_cnt;
   reg    system_reset=1'b0;

    // Reset Counter to give active high reset to enable offset cancellation
counter_128 cnt_128_isnt (
.clock (C100mhz),
.q (system_reset_cnt)
);


    always @ (posedge C100mhz)
    begin
       if (system_reset_cnt >= 8'd128)
           begin
              system_reset <= 1'b1;
           end      
    end

low_latency_10g_1ch DUT (
.refclk_in_clk (C64453mhz),
.clk_50_clk (C100mhz), 
.refclk_reset_reset_n (system_reset),
.clk_50_reset_reset_n (system_reset),
.xcvr_low_latency_phy_0_tx_serial_data_export (GXB_TXL11),
.xcvr_low_latency_phy_0_rx_serial_data_export (GXB_RXL11),
.xcvr_low_latency_phy_0_tx_ready_export (tx_ready),       
.xcvr_low_latency_phy_0_rx_ready_export        (rx_ready),       
.xcvr_low_latency_phy_0_pll_locked_export (pll_locked),
.alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy (reconfig_busy)
);
// 1ch passing 30/9/2011

endmodule

[Kshitij_Intel]

Hi,

1. Which Operating system you are using?
2. Which Quartus Software version you are using?
3. Which device (OPN) you are targeting?
4. Which FPGA Development Kit you are using, if any?

Also, it will be good if you share your Quartus Project QAR.

Thank you,

Kshitij Goel

[DeadEnd]

Thank you for your reply.

Below is an answer you asked.

1. Which Operating system you are using?> Window 11 Pro
2. Which Quartus Software version you are using?> Quartus II 14.0
3. Which device (OPN) you are targeting?> Stratix V (5SGXEA7N2F40C2
4. Which FPGA Development Kit you are using, if any?> Please refer to above answers.

And How can I share my QAR file?

This is an open space, so it is difficult to post it, but if you have a way to share it, I'll share it to you.

[Kshitij_Intel]

Hi Junsu Lee,

Thank you for sharing the design on email. Please allow me some time to look into it and if I need anything else will let you know.

Thank you,

Kshitij Goel

[Kshitij_Intel · Accepted solution]

Hi Junsu,

I have explored and gone through your design, it seems currently 644.53125MHz is coming from an external source pin. If yes, then is it possible to change that clock? I don’t think. Currently you are using clock source of 625MHz which is fed as refclk to XCVR IP. So, if you change the clock accordingly you need to configure the clock source as well. Also, you need to change the Low Latency PHY Intel FPGA IP Configuration accordingly.

If you any questions or want to discuss further, please let me know we can have a call to discuss.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi Junsu,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel