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Node Finder Signal Tap

ee555
Beginner
785 Views

Hi All,

I'm trying to add signals to my .stp file using node finder with the pre-synthesis filter but I'm not able to find the signal I'm looking for.

When I search for the exact signal name I'm looking for, no matches are found.

 

When I search with the wildcard character I see hundreds of these i nodes which I think represent the bits of the signals I want to add.

Capture1.PNG

Does anyone know what these i signals are and what they mean? Also how can I make sure my signals don't get converted to i signals?


One workaround I found was to make these signals into ports. Once these signals are ports then I can find them when I search the exact signal name in node finder but I feel like there is a better way of doing this.

 

Thanks.

 

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sstrell
Honored Contributor III
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Where is the signal in your design hierarchy?  You have a path filled in in "Look in" so it's only going to search at that level of your hierarchy.  If you want to search there and below, turn on "Include subentities".  Change "Look in" to your top-level design with "Include subentities" turned on to search the entire design.  You should also turn on "Hierarchy view" because it makes it much easier to see where found nodes live in your design.

As for what you've found there, they are probably internal nodes created from your RTL.  Scrolling around should show signals that you recognize.  But adjusting "Look in" is probably your best bet.

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ee555
Beginner
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The signal I'm searching for is declared inside the u_ctrl module in the path I have listed in "Look in".  I verified this is the correct spot because I'm able to find other signals from u_ctrl module in node finder. Also, when I updated u_ctrl module to make the signals in question output ports, they appear again in the node finder under the same "Look in" path but I think there is a better way to find the signals I'm looking for.


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sstrell
Honored Contributor III
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Hmm.

You should not have to set the signals as outputs for pre-synthesis signal tapping.  I'd try turning on "Include subentities" just in case if for some reason the tool is thinking they are one level down.

I'd also try setting "Look in" to one level above with "Include subentities" turned on as well.

Post-fit nodes may not appear for a number of reasons using the post-fit filter, but anything in your code should show up with the pre-synthesis filter.

You don't say what version of Quartus this is, but you may also want to click "Customize" and make sure you haven't made adjustments to the pre-synthesis filter.

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ee555
Beginner
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I am using Quartus Prime Version 21.4.0 Build 67

 

I tried going up a level in my design searching with include subentities and the signals I'm looking for still do not appear. 

When I made the signals  output ports, they appear in the node finder. I opened up the RTL viewer and I see the i signals connected to an input of a flop which its output is the signal I'm looking for. See below:

 

Capture.PNG

When  a_count_ovf_q and a_count_q  are not output ports I am able to see these signals in the node finder. 

For more context these are counter signals from a basic upcounter that gets updated in a process whenever a certain pulse goes high. 

Also, I noticed that when these counter signals are not declared as output ports and I look in the RTL viewer, the logic in the above photo doesn't seem to exist. Is it just getting optimized out which is why I'm not seeing it in node finder?

 

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ShengN_Intel
Employee
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sstrell
Honored Contributor III
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The OP is trying to tap pre-synth signals, so while preserve for debug is a good idea for tapping post-fit nodes, it doesn't really help solve the issue.

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ShengN_Intel
Employee
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Hi,

 

Then may be can try with the preserve or noprune attribute in the second link posted https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/preserve-for-debug-overview.html

Preserve link https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_preserve.htm

Noprune link https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_noprune.htm

 

I had tried with a sample code and I can find the signal in signal-tap check screenshot below:

Code:

entity example_module_vhdl is

  port (

    a, b : in std_logic

  );

end entity example_module_vhdl;

architecture Behavioral of example_module_vhdl is

  signal and_result : std_logic;

attribute noprune: boolean; 

attribute noprune of and_result: signal is true;

begin

  process(a, b)

  begin

    and_result <= a and b;

  end process;

end architecture Behavioral;

Screenshot:

ShengN_Intel_0-1711603336018.png

 

Thanks,

Regards,

Sheng

 

 

 

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ShengN_Intel
Employee
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Hi,


May I know do you need any further help on this thread? Does the problem resolved?


Thanks,

Regards,

Sheng


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