Place region and Route region of Quartus Partial Reconfiguration

[dj-park]

I've noticed that there are "Place region" and "Route region" in Quartus Partial Reconfiguration(PR).

I have three related questions.

1) Is the PR persona's routing fully encapsulated in the Route region?

2) There exist "Reserved Placement" and "Reserved Routing" in Logic Lock Regions Properties window as shown below.
If the Place region and Route region are identical (without any Route region's expansion),
"Reserved Routing" setting below is inferred, right?

EDIT: In fact, "Reserved Routing" setting, which creates

RESERVE_ROUTE_REGION ON in the .qsf file, seems to do something different from

the description above because I gave it a try and the routing phase takes more than 30 min(still not finished)

for the design that took 3 min for routing before.

What does RESERVE_ROUTE_REGION ON exactly do?

3) The static design can use routing resources in the PR regions, right?

(I am not sure this is explicitly stated in the PR user guide.)
Is there any simple setting that we can prevent the static design to borrow even the routing resources in the PR region so that static design and PR Personas are isolated?

I am kind of new to Intel FPGA, but this forum has been very helpful. Thanks.

[sstrell]

1) Yes.  The routing region extends around the placement region.  Usually you set the size of it to be just 1 block larger than the placement region (fixed with expansion = 1).

2) Reserved routing is not inferred.  As the option says, if that's turned off, the Fitter is free to place other design logic in the routing region.  Turning it on prevents that from happening, making the region boundary completely prevent outside logic from being placed in there.  If it's taking you that much longer to compile, your region placement perhaps is blocking access to certain resources needed for the rest of the design.  Hard to tell.

3) Yes, routing for the static region can still go through the PR region.  I don't think it's possible to prevent this.  It would potentially add a lot of extra delay to route around a region.

[dj-park]

Thanks to the reply. 1) and 3) are resolved.

2) Yes, I understand what the option says. But let's say that we create the exact same size of Route region as Place region(fixed with expansion = 0). Then, if "Reserved Placement" setting is on, it prevents the outside logic from being placed in the Place region, and because Place region is the same as Route region, it prevents the outside logic from being placed in the Route region too. This is why I assume that if they are equal-sized, "Reserved Routing" is inferred from "Reserved Placement."

However, in the experiment that I have the same Place region and Route region, "Reserved Routing" seems to do something different. Based on the option description, it should do the exact same thing as "Reserved Placement" in this case. My guess is that it might do something similar to my question on 3)... For instance, "Reserved Routing" may be the option to prevent static routing to use routing resources in the PR region?

[sstrell]

Hmm, that reserved routing option is relatively new (I haven't done much PR stuff since 2020 so I know this option wasn't there back then) and I haven't played with it so you may be right.  Maybe the description is supposed to say "Prevent Fitter from placing non-member *routing* in routing region".

[dj-park]

Yeah, something like that... I am not sure. But thanks a lot!!

[RichardTanSY_Intel]

Agree with Strell, the RESERVE_ROUTE_REGION should be similar to RESERVE_PLACE_REGION making the region exclusive to only the contents assigned to it.

Best Regards,

Richard Tan

[dj-park]

@RichardTanSY_Intel Thanks for the reply.

Then, what do you think is the expected behavior when the Place_region is the same as the Route_region(the scenario I mentioned above)?

[RichardTanSY_Intel]

Though it is similar to the reserved placement region, the RESERVED_ROUTE_REGION assignment reserves all the routing within the logic lock region(LLR) for paths assigned to that LLR. While RESERVED_PLACE_REGION reserves all the placement assigned to that LLR.

A little bit of background history, this feature does not work as expected and was drop in 2018. Then it was brought back in 2019 as there a couple of use cases, though niche, that can benefit from it. Like static region crosstalk problems. There is side effect as you can see in the warning message pop up when you check the box. So use only if strictly necessary.

All in all, I will avoid using that.

Best Regards,

Richard Tan

[dj-park]

Thanks. Your answer is in fact consistent with my guess above.
I think RESERVED_ROUTE_REGION reserves routing and placement logic in the PR region.

Interesting history! Can you elaborate on "static region crosstalk problem?"
Do you mean that if too much static routing goes over the PR region, there exists less routing resource left for the PR region?

[RichardTanSY_Intel]

There is potential crosstalk effect between the static region and PR region. By reserved the route region, it may helps to prevent the static region from having any aggressors in a PR region.

To know more about the crosstalk, you may check out in wiki or IEEE paper (if you have access).

https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1219156

Best Regards,

Richard Tan

[dj-park]

Thanks for the information. This was really helpful.

[RichardTanSY_Intel]

Great to hear that! I hope the information benefits you.

I believe your inquiry has been answered, with that, I now transition this thread to community support. 

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[dj-park]

For those of you who are interested, in my experiment, RESERVE_ROUTE_REGION does NOT prevent the static routing in the PR regions. I am experimenting with Quartus Prime Pro Edition 22.2 with Agilex device.

I am not sure there's a feature to see routing only in Chip Planner, but looking at "Report Routing Utilization", static routing crosses

PR regions that have "RESERVE_ROUTE_REGION" ON.

Also in AN 307: Intel® FPGA Design Flow for Xilinx* Users, RESERVE_ROUTE_REGION is missing for some reason...