PreLoader for HPS loan IO

[Mahsheed]

I am using DE10 Nano, and I want to loan IO from HPS to FPGA. I have generated HDL file from Qsys and added SoC_system.v file in my top level file in FPGA.
  But I do not know how to custom set the HPS registers in the preloader. I have never added preloader before, so I am blank here. I can share the BSP editor screen shot here. If anyone can please guide me how to link it with Qsys generated file to tell the preloader to set registers according to the design. Because HDL generated file goes directly into FPGA, leaving nothing for HPS preloader to configure. Thanks in advance

[khtan]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

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[JingyangTeh]

Hi

For the Perloader build , there have been a change in the build flow.

You could find out more from the link below:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10

In short the BSP-Editor is no longer in used and only used to generate the files core files that link the Hardware design from the quartus to the bootloader.

Changes are not to be made in the BSP-editor.

Regards

Jingyang, Teh

[Mahsheed]

I am actually using Quartus 16. So I loaned IO of Ethernet PHY pins from HPS to FPGA using the .qar file given in below link

https://community.intel.com/t5/FPGA-Wiki/Using-HPS-IO-in-Cyclone-V-and-Arria-V/ta-p/735656#:~:text=The%20loaner%20I%2FO%20ports,ARM%20Hard%20Processor%20Subsystem%20block.

Once, I generated my qsys system, I used BPS editor to create MPL by following the instructions given in the video link below

https://www.intel.com/content/www/us/en/content-details/649272/how-to-build-the-minimal-preloader-mpl.html

Once generated, I used the the win32Disk Imager and used the facility alt-boot-disk-util.exe to add the preloader .bin file into the SD card.

When I added the Preloader file, my Linux didn't boot. Which implies that updated preloader was working, as my U-boot might not have run successfully and by Device tree is not updated as well.

But my main issue is that I didn't get any thing on my receive data or receive packet valid of my TSE IP core pins (I tried sending data over UDP from my PC)

Also, Ethernet port green light was constant on even if I do not plug in the SD card. Which is weird too that how come it established the Network connection without booting HPS Linux or initialization from FPGA.

If anyone has any idea, what exactly I am missing in making it work. Please let me know. Thanks in advance. 

[JingyangTeh]

Hi

From the looks of it the MPL will not boot into Linux.

It will boot into the MPL and stay there.

Just to inform you that the MPL software is no longer supported.

It is advisable to follow the latest version Quartus to build as mentioned in RockeBoard.

Regards

Jingyang, Teh

[Mahsheed]

Hello,
Extremely sorry for the delayed response, as I was away from the internet for the past couple of days.

The problem is that I have setup my whole project in Quartus 16. changing it to the latest would be very cumbersome. If you could only help me with the LoanIO of PHY pins, I would be highly greatful to you.

If MPL stays there, it must have initialized the HPS for the necessary Loan IO configurations.

If this happens and using the already built project of loan IO for data sending/receiving over Ethernet should work. If you could guide me what part I am missing in this whole scenario which doesn't let me access ethernet over FPGA. Thanks in advance.

[JingyangTeh]

Hi

Do you have any update for this case?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

After the MPL loaded, is there an application that interface with the Ethernet port?

Once the MPL have initialized the HPS IOs if there are no application that interface with the IOs, it will be left as it is.

Regards

Jingyang, Teh

[Mahsheed]

Since I have tried loaning IO pins from HPS to FPGA in the QSYS, which in turn is reflected in my updated MPL. So, I am using TSE IP Core in my FPGA side to send and receive the data over UDP. I simply tried if I am receiving anything at my receive pins of TSE IP core (which should be linked with my Loan IO PHY pins). But I didn't receive anything when I sent data to DE10 Nano from my pc over Ethernet using UDP protocol.

[JingyangTeh]

Hi

I am having a hard time understanding your connection.

Could you share me your quartus project?

Are you running a baremetal project on the HPS ?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh