Problem with: Start compilation

[Altera_Forum]

Hi to everyone, 

I have a problem when i do Start Compilation and i don't know how to do to solve this problem. I'm posting the log and i hope someone can help me because i have to do a project for a univesity homework.   Internal Error: Sub-system: SUTIL, File: /quartus/synth/sutil/sutil_device.cpp, Line: 1242 is_legal_device() Stack Trace:  0x9702: MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem)  0xa268: mem_realloc_wrapper + 0x188 (ccl_mem)  0x5580: mem_out_of_memory + 0x4f0 (ccl_mem)  0x82c5: MEM_SEGMENT_INTERNAL::allocate + 0x95 (ccl_mem)  End-trace  Quartus II Version 9.1 Build 304 01/25/2010 SJ Web Edition Service Pack Installed: 1     Can someone help me ?

[Altera_Forum]

I have olso tryied with the service pack 2 but the error is the same: 

  Internal Error: Sub-system: SUTIL, File: /quartus/synth/sutil/sutil_device.cpp, Line: 1242 is_legal_device() Stack Trace:  0x9702: MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem)  0x9d58: MEM_SEGMENT_INTERNAL::locked_allocate + 0x6b8 (ccl_mem)  End-trace  Quartus II Version 9.1 Build 350 03/24/2010 SJ Web Edition Service Pack Installed: 2

[Altera_Forum]

which device are you targeting? there's a clue about a problem in is_legal_device().

[Altera_Forum]

The Family Device which i selected is Stratix II and the Target Device: Auto device selected by the Fitter. It's all right until i do the the Functional simulation, but when i set to Timing and i do Start Compilation then appear a window error. The window error is still the same: 

  Internal Error: Sub-system: SUTIL, File: /quartus/synth/sutil/sutil_device.cpp, Line: 1242 is_legal_device() Stack Trace:  0x9702: MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem)  0x9d58: MEM_SEGMENT_INTERNAL::locked_allocate + 0x6b8 (ccl_mem)  End-trace  Quartus II Version 9.1 Build 350 03/24/2010 SJ Web Edition Service Pack Installed: 2

[Altera_Forum]

i was not able to reproduce this on 9.1sp2 for Linux (subscription edition, web edition does not have the Quartus Simulator). 

 in web edition you may have to select one of the two supported SII parts to do a full compile:   Stratix II / II GX FPGAs: EP2S15, EP2SGX30  from the Quartus II web edition and subscription edition comparison:  http://www.altera.com/literature/po/ss_quartussevswe.pdf

[Altera_Forum]

--- Quote Start ---  i was not able to reproduce this on 9.1sp2 for Linux (subscription edition, web edition does not have the Quartus Simulator).  in web edition you may have to select one of the two supported SII parts to do a full compile:   Stratix II / II GX FPGAs: EP2S15, EP2SGX30    --- Quote End ---     Thank you so much thepancake, thanks to your suggest i found the problem. The problem was that i had done a custom istallation and i selected only the basic tools and so no one of Stratix II devices driver were installed. So i have done a complete istallation and now i can do olso a Timing simulation. I apologise 4 my english. Thank you again Good Bye