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Quartus Error - Simulated vs Expected Result

Altera_Forum
Honored Contributor II
‎02-06-2008 01:36 PM
1,108 Views

Hello all,  

 

I am a newbie to Quartus and VHDL. I am getting an error when trying to simulate a VHDL code. It compiles successfully though.  

 

The error is "Simulation results do not match expected results from vector source file".  

 

Can someone please explain what it means? What are the 'expected results'? I have not defined any expected results prior to simulation !  

 

Many Thanks, 

Farrukh
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Altera_Forum
Honored Contributor II
‎02-07-2008 01:50 AM
396 Views

Hi, 

 

There is a check box in the simulation settings that makes the simulator check the VWF file with the simulation result, to see if there is any difference. This can be really handy if you know the resulting waveforms you are after. You dont need to go through and check it, the tool will just tell you.
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Altera_Forum
Honored Contributor II
‎02-07-2008 09:18 PM
396 Views

Thnks! It works !!

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