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Quartus Prime Light Waveform Simulation Error

TileSeeker
Novice
2,415 Views

Hello, I am having trouble with running timing and functional simulations in the Simulation Waveform Editor.

I have been following a a tutorial described in the book "Circuit Design With VHDL" by Volney A. Pedroni. The tutorial detailes the step-by-step instructions for creating ans simulation a registered adder in VHDL. I have Succsessfully compiled the code and viewed the Netlist in RTL and TM viewer, but I am getting an error when I try to simulations in the Simulation Waveform Editor.

This is the error message i get:

# ** Error: Waveform.vwf.vht(127): near "~": syntax error

# ** Error: Waveform.vwf.vht(134): near "~": syntax error

# ** Error: Waveform.vwf.vht(141): near "~": syntax error

# ** Note: Waveform.vwf.vht(144): VHDL Compiler exiting

# End time: 22:24:20 on Aug 18,2022, Elapsed time: 0:00:00

# Errors: 3, Warnings: 0

# ** Error: C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vcom failed.

# Executing ONERROR command at macro ./registered_adder.do line 4

 

Error.

 

This is what the editor looks like. I have not changed any of the default Simulation settings:

TileSeeker_1-1660854380875.png

 

This is my the full VHDL code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity registered_adder is
port (
clk: in std_logic;
a, b: in std_logic_vector(2 downto 0);
sum, sum_reg: out std_logic_vector(3 downto 0));
end entity;

architecture rtl of registered_adder is
begin
sum <= std_logic_vector( ('0' & unsigned(a)) + unsigned(b) );

process(clk)
begin
if rising_edge(clk) then
sum_reg <= sum;
end if;
end process;
end architecture;

This is the RTL Viewer:

TileSeeker_2-1660854497559.png

 

I am very new to this, so I would appreciate as much help as I can get

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8 Replies
ShengN_Intel
Employee
2,385 Views

Hi,


Try with these devices Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, MAX II, MAX V, Stratix IV and set Target device to Auto device selected by the Fitter. Recompile and recreate the .vwf file. Also in Simulation Waveform Editor, go to Simulation > Simulation Settings and delete -novopt then save.

Some of the devices are not supported by Simulation Waveform Editor since it's old version simulator.


Best Regards,

Sheng


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


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TileSeeker
Novice
2,374 Views

I think i did what you suggested, but it didn't fix the problem.

i was a but unsure about what you ment by delete the "-novopt". I went to Simulation > Simulation Settings and deleted "-novopt" on the fith line of the ModelSim Script editor (The place marked with -novopt). This is what it looks like now:

onerror {exit -code 1}

vlib work

vcom -work work registered_adder.vho

vcom -work work Waveform.vwf.vht

vsim -novopt -c -t 1ps -sdfmax registered_adder_vhd_vec_tst/i1=registered_adder_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.registered_adder_vhd_vec_tst

vcd file -direction registered_adder.msim.vcd

vcd add -internal registered_adder_vhd_vec_tst/*

vcd add -internal registered_adder_vhd_vec_tst/i1/*

proc simTimestamp {} {

echo "Simulation time: $::now ps"

if { [string equal running [runStatus]] } {

after 2500 simTimestamp

}

}

after 2500 simTimestamp

run -all

quit -f

 

 

I got the same error as last time:

# ** Error: Waveform.vwf.vht(127): near "~": syntax error

# ** Error: Waveform.vwf.vht(134): near "~": syntax error

# ** Error: Waveform.vwf.vht(141): near "~": syntax error

# ** Note: Waveform.vwf.vht(144): VHDL Compiler exiting

# End time: 18:03:37 on Aug 19,2022, Elapsed time: 0:00:00

# Errors: 3, Warnings: 0

# ** Error: C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vcom failed.

# Executing ONERROR command at macro ./registered_adder.do line 4

 

Error.

 

Do you have any other ideas?

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cristag
Beginner
1,683 Views

I am following the same tutorial, and getting the Error loading design, even if I deleted the -novopt and have no more pins for simulation than clk, a, b, sum and sum_reg. But I have a FPGA MAX 10 10M50DAF484C7G so, just to be clear, I cannot run Simulation with this device, right?

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ShengN_Intel
Employee
2,358 Views

Hi,


Can you share the project file to me for testing out?


Thanks,

Best regards,

Sheng


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TileSeeker
Novice
2,342 Views

Here you go.

*edit: Uploaded tha wrong file. I've fixed it now

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ShengN_Intel
Employee
2,327 Views

~ALTERA_NCEO~

~ALTERA_DATA0~

~ALTERA_ASDO~

~ALTERA_NCSO~

~ALTERA_DCLK~

These are reserved dedicated programming pins. You can't and not necessary to simulate them. Not need to include those pins in Simulation Waveform Editor.


Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


TileSeeker
Novice
2,313 Views

That fixed my problem. Thank you for the help

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Bassam1
Beginner
2,283 Views

I am having this error when I try to simulate a design:

 

# vsim -c -t 1ps -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.dec2to4_vhd_vec_tst

# Start time: 14:32:00 on Aug 23,2022

# ** Note: (vsim-3812) Design is being optimized...

# ** Fatal: Unexpected signal: 11.

# ** Note: Vopt Compiler exiting

# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=0.

 

# Error loading design

 

Error loading design

 

# End time: 14:32:01 on Aug 23,2022, Elapsed time: 0:00:01

# Errors: 1, Warnings: 0

 

Error.

 

The code is very simple one which is given below:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY dec2to4 IS
      PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
             En : IN STD_LOGIC ;
             y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 IS
         SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
           Enw <= En & w ; -- Notice how to combine two signals into one
           WITH Enw SELECT
                  y <= "1000" WHEN "100",
                           "0100" WHEN "101",
                           "0010" WHEN "110",
                           "0001" WHEN "111",
                           "0000" WHEN OTHERS ;
END Behavior ;

 

 

 

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