your design fails timing analysis because Arria 10 maximum core clock frequency of 644 MHz is exceeded (timing analyser uses rounded value of 645.16MHz = 1/1.55ns). This causes a "minimum pulsewidth" violation for clk and a respective restricted Fmax value. Possible contradicting reported values in timing analysis are referred. You need to solve the minimum pulsewidth problem first.
Presume NR_symbol_modulator is planned to be used inside an Arria 10 design with some kind of high speed interface. Consider that FPGA fabric side of the interface can't run above 644 MHz clock. If intended 780 MHz clock is required by interface throughput, you'll need more bits for the parallel data stream.
