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Question Regarding Clock Synchronization in EyeQ BER function

DeadEnd
New Contributor I
657 Views

Hello, I have a question regarding Stratix.

I am looking to measure BER using the EyeQ feature on Stratix. Here’s my question: when Stratix transmits and receives data for BER measurement, it synchronizes with the clock.

Does this synchronization only occur at the clock's rising edge? Or does it not synchronize at the falling edge, similar to DDR?

Additionally, is there a feature in Qsys, IP, or Quartus that enables operation like DDR? I've been searching but can't find any information, so I'm asking here.

Please note that I am using Stratics V and my Quartus version is 14.0.

Thank you for your help!

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1 Solution
Kshitij_Intel
Employee
425 Views

Hi,

I understand, your confusion. My understanding is that from the statement i.e., "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS." it is Single Data Rate Only but width of data and control word becomes double i.e., 64-bit and 8-bit Actually you achieves the same data rate.


So, no need to sample at rising and falling edge for double data rate.


Hope this clarifies.


Thank you,

Kshitij Goel


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7 Replies
Kshitij_Intel
Employee
579 Views

Hi,


It depends on the which protocol you are implementing. Please refer 4.2.2. 10GBASE-R and 10GBASE-KR Supported Features (intel.com) For this protocol it supports DDR mode.


Thank you,

Kshitij Goel


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DeadEnd
New Contributor I
556 Views

Thank you for your reply.

 

But the contents you shared show that "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS."

 

Since BER uses transicever, doesn't that mean DDR is not supported?

If not, I would be very grateful if you could tell me how to determine which protocol I used.

 

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Kshitij_Intel
Employee
426 Views

Hi,

I understand, your confusion. My understanding is that from the statement i.e., "The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and the PCS." it is Single Data Rate Only but width of data and control word becomes double i.e., 64-bit and 8-bit Actually you achieves the same data rate.


So, no need to sample at rising and falling edge for double data rate.


Hope this clarifies.


Thank you,

Kshitij Goel


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DeadEnd
New Contributor I
358 Views

Oh, so the transceiver can get the effect of DDR with just SDR with width of data and control word?
And if so, it sends 64 bits of data in one clock, right?

So does Tranceiver always send 64 bits of data in one clock?

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Kshitij_Intel
Employee
338 Views

Hi,


And if so, it sends 64 bits of data in one clock, right?

--> Yes.

So, does Transceiver always send 64 bits of data in one clock?

--> No, it depends on which protocol you are using. Always refer UG 4.2.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and... (intel.com)


Regards,

Kshitij Goel


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Kshitij_Intel
Employee
269 Views

Hi,


As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

 

Thank you,

Kshitij Goel


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DeadEnd
New Contributor I
254 Views

I apologize for the delay in responding.

I'll do some more research and ask you if you have any additional questions.
Thank you very much for your help.

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