Hi,
I'm having a nightmare in the past 3 days as I'm having a terribly inconsistent behavior from an SCFIFO I'm using to store 8-bit values, on Quartus Prime 18.1, on a Cyclone IV board.
It's a normal synchronous FIFO, 8-bit wide and 128 words deep.
Memory block type is in auto and protection circuity was not disabled, so it shouldn't either overflow nor underflow.
What's happening is that, specially if I enable some of its inputs and outputs in signaltap and compile it, it behaves very inconsistently.
Without anything enabled, there's no issue.
With everything enabled, no issue again.
But enabling only part of the outputs and inputs, it becomes inconsistent.
Right now, the all but the data output (q) are enabled on signal tap.
The first error was that the write request was making it empty instead of filling.
So usedw would start on 0 and then it would underflow to 127, which it shouldn't even do once it's protected.
And no, there was nothing on the rdreq line at any moment.
This also made the FIFO turn its full flag on, but without turning empty off, both kept on 1 until the next write request, which made usedw fall to 126 and both flags go to 0. But the following write requests didn't change usedw, it locked on 126.
If the FIFO wasn't empty in the beginning, say it had 30 words on it, the write requests would empty word by word and then cause this same problem when it reached 0.
Now I added the option to flush it using sclr, and I flush it a couple cycles before starting to write, plus added it to signaltap.
Now the inconsistency is different.
Most of the times now it will work normally, but about 1/10 of the times the flush will suddenly make it full (???) and then when the next write request comes, it overflows to 0 and lock up, doesn't write anything on it until the next attempt, when it's flushed again.
And sometimes it will also go to zero with the flush, only to again empty with the next write request.
I sincerely can't figure out what is happening here.
And I know this isn't any issue with my code, because then I'd see something wrong when looking on signaltap, but what signaltap itself is showing is total nonsense.
I tried checking that option to use only logic cells and no memory blocks, and the only thing it changed is that now full and empty flags always keep on 0, plus it doesn't lock after underflowing now, it keeps decreasing at every write request.
Here's a picture of what it's doing:
The rest doesn't change.
What else can I try? Except for just accepting I can't see anything on it with signaltap, because it works if I don't.
I'm starting to suspect I'm doing quantum computing here.
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