When a PLL has multiple reference clock inputs how can you define the one to use for timing analysis? The tool is selecting the first reference clock (pll_refclk0) for timing analysis but this is the slower of two reference clocks. The clock inputs cannot be swapped in the RTL as the slower clock is running when the PLL and transceivers are configured.
Depending on your device, you should always just use derive_pll_clocks in your .sdc and the generated clocks created by that command. Newer devices support this without you adding it explicitly to the .sdc file.
You may also check your timing report, some of the device like Agilex 7, the derive_pll_clocks is auto inserted. Do let me know if you have further question?
I have been using derive_pll_clocks but it uses the slower of the two input clocks for timing analysis. The clock tree analysis shows this. Reporting the timing of any path clocked by the output of the PLL also shows that it is using the slower clock period. The device is an Arria 10.
I'm not sure why the source clock used matters here, but you could manually add create_generated_clock commands to your .sdc to define the correct source clock for the clock in question if derive_pll_clocks is using the wrong source.
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