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In logic simulation, I can capture the output of ALTSDDIO_OUT. However, in SignalTap, I can capture the inputs data_h and data_l, but I cannot capture the output. I have tried various clock and reset signal configurations, but it still doesn't work.
Is it because SignalTap cannot capture this type of dual-edge signal?
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No, it's because Signal Tap can't connect directly to I/O outputs because there's no signal wire back into the core to connect to Signal Tap. You have to tap whatever is feeding into the output, like data_h and data_l as you mention.
In the Node Finder, when adding signals to Signal Tap, you should be using one of the Signal Tap filters. This makes sure you tap only signals that are "tappable" to Signal Tap. Outputs would not show up in this filter.
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No, it's because Signal Tap can't connect directly to I/O outputs because there's no signal wire back into the core to connect to Signal Tap. You have to tap whatever is feeding into the output, like data_h and data_l as you mention.
In the Node Finder, when adding signals to Signal Tap, you should be using one of the Signal Tap filters. This makes sure you tap only signals that are "tappable" to Signal Tap. Outputs would not show up in this filter.
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Alright, what I understand is that I cannot directly capture the output of DDIO, but can have an appropriate external processing for this signal and then capture it indirectly. Thank you for your response.
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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