Sof build failing in Fit stage with the following build message "Final fitting attempt was unsuccess

[ranga]

Warning (16618): Fitter routing phase terminated due to routing congestion. Congestion details can be found in Chip Planner.
Critical Warning (188026): The Fitter failed to successfully route the design. View the Global Router Wire Utilization Map in the reports GUI and/or Routing Utilization in the Chip Planner to diagnose routing congestion. Based on the congestion information, modify your RTL or compiler settings to improve routability. Consult Intel Quartus Prime help about this message ID for more detailed advice

Error (170143): Final fitting attempt was unsuccessful

@SivaKona 

[sstrell]

As the message states, you have too much routing in your design for whatever device you are targeting.

[RichardTanSY_Intel]

Bookmark this main page for future reference in case you need to get more detail information on how to solve upcoming errors:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/wvpr20k_vpr_no_route_suggestion_message.htm

ID:188026 The Fitter failed to successfully route the design. View the Global Router Wire Utilization Map in the reports GUI and/or Routing Utilization in the Chip Planner to diagnose routing congestion. Based on the congestion information, modify your RTL or compiler settings to improve routability. Consult Intel Quartus Prime help about this message ID for more detailed advice.

CAUSE: The Fitter was unable to route the design because it requires too many device routing resources.

ACTION: There are multiple ways to diagnose or resolve a routing problem. Use one of the following methods to diagnose the routing problem:

• View the Global Routing Wire Utilization Map in GUI for overall routing congestion.
• View the Report Routing Utilization in Chip Planner for detailed routing congestion.
• Investigate signals identified by the router.
• Turn off timing optimization or alternatively just hold optimizations to see if timing constraints are the issue.
• Investigate non-global large fanout nets.

Use one of the following methods to resolve the routing problem:

• Reduce routing demand by modifying the design. Reduce the interconnect complexity by localizing routing as much as possible. For example, transform a cross-bar interconnect into a ring-style interconnect to reduce interconnect complexity and improve routability (at the cost of increasing latency).
• If a global signal is unroutable, then delete global promotion of that signal.
• Add or remove Logic Lock regions.
• Reduce very aggressive timing constraints.
• Cut timing paths on cross-clock transfers.
• Change the Fitter Initial Placement Seed in the Advanced Fitter Settings dialog.
• Enable the Fitter Aggressive Routability Optimizations logic option in the Advanced Fitter Settings dialog.
• Reduce logic utilization.
• Select a larger device.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

[RichardTanSY_Intel]

May I know does my latest reply help to answer your question?

Do you need further help?

Best Regards,

Richard Tan

[RichardTanSY_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

[ranga · Accepted solution]

Hi @RichardTanSY_Intel  and @sstrell,

Thank you for the reply.  We tried to solve our problem by reducing the number of memories we use in the design. That was causing this issue. Thank you once again.